Renesas PFESiP/V850EP1 User Manual page 28

32-bit microcontroller dedicated to pfesip ep-1
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(2) SDRAM access timing
Parameter
Address delay time (from BUSCLK↑)
BCYSTZ delay time (from BUSCLK↑)
Note
CSZn
delay time (from BUSCLK↑)
SDRASZ delay time (from BUSCLK↑)
SDCASZ delay time (from BUSCLK↑)
SDWEZ delay time (from BUSCLK↑)
DQM0-DQM3 delay time (from BUSCLK↑)
SDCKE delay time (from BUSCLK↑)
Data input setup time (SDRAM read, from BUSCLK↑)
Data input hold time (SDRAM read, from BUSCLK↑)
Data output delay time (from BUSCLK↑)
Data float delay time (from BUSCLK↑)
REFRQZ time (from BUSCLK↑)
Note
n = 1, 3, 4, 6
26
CHAPTER 1 PRODUCT SPECIFCATIONS
Table 1-13. SDRAM Access Timing
Symbol
t
DKA
t
DKBC
t
DKCS
t
DKRAS
t
DKCAS
t
DKWE
t
DKDQM
t
DKCKE
t
SKDRM
t
HKDRM
t
DKDT1
t
DKDT2
t
HZKDT
t
DKREF
User's Manual A19069EJ2V0UM
MIN.
MAX.
1.5
11.0
1.5
9.0
1.5
11.0
1.5
11.0
1.5
11.0
1.5
11.0
1.5
11.0
1.5
11.0
3.8
1.0
1.5
11.0
1.5
11.0
1.5
11.0
1.5
11.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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