Pci Express Edge Connector - Xilinx KC705 User Manual

Table 1-10: GTX Interface Connections for FPGA U1 (Cont'd)
Transceiver Bank
MGT_BANK_116
MGT_BANK_117
MGT_BANK_118
For more information on the GTX transceivers, see 7 Series FPGAs GTX Transceivers
User Guide (UG476)

PCI Express Edge Connector

[Figure 1-2, callout 13]
The 8-lane PCI Express edge connector performs data transfers at the rate of 2.5 GT/s for a
Gen1 application and 5.0 GT/s for a Gen2 application. The PCIe transmit and receive signal
datapaths have a characteristic impedance of 85Ω ±10%. The PCIe clock is routed as a 100Ω
differential pair. The 7 series FPGAs GTX transceivers are used for multi-gigabit per second
serial interfaces.
The XC7K325T-2FFG900C FPGA (-2 speed grade) included with the KC705 board supports
up to Gen2 x8.
KC705 Evaluation Board
UG810 (v1.8) March 20, 2018
Associated Net Name
GTXE2_CHANNEL_X0Y4
GTXE2_CHANNEL_X0Y5
GTXE2_CHANNEL_X0Y6
GTXE2_CHANNEL_X0Y7
MGTREFCLK0
MGTREFCLK1
GTXE2_CHANNEL_X0Y8
GTXE2_CHANNEL_X0Y9
GTXE2_CHANNEL_X0Y10
GTXE2_CHANNEL_X0Y11
MGTREFCLK0
MGTREFCLK1
GTXE2_CHANNEL_X0Y12
GTXE2_CHANNEL_X0Y13
GTXE2_CHANNEL_X0Y14
GTXE2_CHANNEL_X0Y15
MGTREFCLK0
MGTREFCLK1
[Ref 12].
www.xilinx.com
Chapter 1: KC705 Evaluation Board Features
Connections
FMC LPC GBT_CLK0
FMC LPC DP0
SGMII_CLK
SMA_CLK
FMC HPC DP0
FMC HPC DP1
FMC HPC DP2
FMC HPC DP3
FMC HPC GBT_CLK0
FMC HPC GBT_CLK1
Send Feedback
PCIe3
PCIe2
PCIe1
PCIe0
Si5326
SMA
SGMII
SFP+
35