Getting Started With Pci Express Pio Demonstration - Xilinx Virtex-6 FPGA ML605 Getting Started

Getting Started with PCI Express PIO Demonstration

Getting Started with PCI Express PIO Demonstration
The LogiCORE™ IP Virtex-6 Integrated Block for PCI Express® core is a high-bandwidth,
scalable, and reliable serial interconnect building block for use with Virtex-6 FPGA
devices. The Integrated Block for PCI Express solution supports 1-lane, 2-lane, 4- lane, and
8-lane Endpoint and Root Port configurations at up to Gen2 speed, all of which are
compliant with the PCI Express Base Specification, v2.0.
For information about the internal architecture of the Virtex-6 FPGA Integrated Block, see
the LogiCORE™ IP Virtex-6 FPGA Integrated Block User Guide for PCI Express.
Figure 1-27
X-Ref Target - Figure 1-27
User
Logic
Physical Layer
Control and Status
Host
Interface
User
Logic
The ML605 x8 PCI Express Gen 1 Programmed Input Output (PIO) design consists of a
simple example that can accept read and write transactions and respond to requests. PIO
transactions are generally used by a PCI Express system host CPU to access Memory
Mapped Input Output (MMIO) and Configuration Mapped Input Output (CMIO)
locations in the PCI Express fabric. Endpoints for PCI Express accept Memory and IO
Write transactions and respond to Memory and IO Read transactions with Completion
with Data transactions.
The ML605 PIO example design is included with the Endpoint for PCIe generated by the
CORE Generator, which allows users to easily bring up their system board with a known
established working design to verify the link and functionality of the board.
The step-by-step procedure for creating the PIO design by Xilinx CORE Generator™
software is illustrated by the ML605 PCIe x8 Gen1 Design Creation tutorial
http://www.xilinx.com/products/devkits/EK-V6-ML605-G.htm.
28
illustrates the interfaces to the core.
LogiCORE IP Virtex-6 FPGA
Integrated Block for PCI Express
TX RX
Block RAM Block RAM
Transaction
(TRN)
Virtex-6 FPGA
Physical
(PL)
Integrated Block for
PCI Express
(PCIE_2_0)
Configuration
(CFG)
Optional Debug
(DRP)
Figure 1-27: Interfaces to the Core
www.xilinx.com
PCI Express
(PCI_EXP)
GTX
Transceivers
Optional Debug
System
(SYS)
Virtex-6 Getting Started Guide
UG533 (v1.4) November 15, 2010
[Ref 18]
PCI
Express
Fabric
User Logic
Clock
and
Reset
UG533_11_101609
[Ref 23]. See