Pci Express Interface - Xilinx ML505 User Manual

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40. PCI Express Interface

ML505/ML506/ML507 Evaluation Platform
UG347 (v3.1.1) October 7, 2009
Downloaded from Elcodis.com electronic components distributor
Table 1-25 shows the PCIe connector (P21) that provides single-lane access through the
RocketIO transceivers to the Virtex-5 FPGA integrated Endpoint block for PCIe designs.
See the Virtex-5 FPGA Integrated Endpoint Block User Guide for PCI Express Designs
more information.
Table 1-25: PCIe Connection to FPGA
FPGA Pin
Pin Name
(U1)
PCIE_RX_N AF1
PCIE_RX_P AE1
PCIE_TX_N AE2
PCIE_TX_P AD2
PCIE_CLK_N AF3
PCIE_CLK_P AF4
PCIE_PRSNT_B AF24
PCIE_PERST_B -
PCIE_WAKE_B -
Notes:
1. For ML505/ML506 platforms, access is through GTP0 of GTP_X0Y1.
2. For ML507 platforms, access is through GTX0 of GTX_X0Y2.
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Edge
Connector Pin
(P21)
B15
Integrated Endpoint block receive pair
B14
A17
Integrated Endpoint block transmit pair
A16
A14
Integrated Endpoint block differential
clock pair from PCIe edge connector
A13
A1, B17 Integrated Endpoint block present signal
Integrated Endpoint block reset signal
A11
available on CPLD
Integrated Endpoint block wake signal
B11
available on CPLD
Detailed Description
[Ref 11] for
Description
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