Xilinx VC707 User Manual page 88

Appendix C: Master UCF Listing
NET FMC1_HPC_HB05_N
NET FMC1_HPC_HB12_P
NET FMC1_HPC_HB12_N
NET FMC1_HPC_HB00_CC_P
NET FMC1_HPC_HB00_CC_N
NET FMC1_HPC_HB17_CC_P
NET FMC1_HPC_HB17_CC_N
NET FMC1_HPC_HB06_CC_P
NET FMC1_HPC_HB06_CC_N
NET FMC1_HPC_HB10_P
NET FMC1_HPC_HB10_N
NET FMC1_HPC_HB19_P
NET FMC1_HPC_HB19_N
NET FMC1_HPC_HB11_P
NET FMC1_HPC_HB11_N
NET FMC1_HPC_HB15_P
NET FMC1_HPC_HB15_N
NET FMC1_HPC_HB20_P
NET FMC1_HPC_HB20_N
NET FMC1_HPC_HB13_P
NET FMC1_HPC_HB13_N
NET FMC1_HPC_HB21_P
NET FMC1_HPC_HB21_N
NET FMC1_HPC_HB16_P
NET FMC1_HPC_HB16_N
#NET 9N473
#NET 9N474
#NET 9N475
#NET 9N476
#NET 9N477
#NET VRN_37
NET DDR3_D32
NET DDR3_D38
NET DDR3_D37
NET DDR3_D36
NET DDR3_DQS4_P
NET DDR3_DQS4_N
NET DDR3_DM4
NET DDR3_D33
NET DDR3_D35
NET DDR3_D34
NET DDR3_D39
#NET VTTVREF
NET DDR3_D44
NET DDR3_D40
NET DDR3_D46
NET DDR3_D47
NET DDR3_DQS5_P
NET DDR3_DQS5_N
NET DDR3_D45
NET DDR3_D41
NET DDR3_DM5
NET DDR3_D42
NET DDR3_D43
#NET 9N541
NET DDR3_D49
NET DDR3_D52
NET DDR3_D51
NET DDR3_RESET_B
NET DDR3_DQS6_P
NET DDR3_DQS6_N
NET DDR3_D54
NET DDR3_D55
NET DDR3_D50
NET DDR3_D48
NET DDR3_DM6
NET DDR3_D53
NET DDR3_D56
#NET VTTVREF
NET DDR3_D63
NET DDR3_D60
NET DDR3_DQS7_P
NET DDR3_DQS7_N
NET DDR3_D57
NET DDR3_D61
NET DDR3_D62
NET DDR3_D59
NET DDR3_D58
NET DDR3_DM7
#NET VRP_37
#NET VRN_38
88
LOC = J27 | IOSTANDARD=LVCMOS18; # Bank
LOC = K24 | IOSTANDARD=LVCMOS18; # Bank
LOC = K25 | IOSTANDARD=LVCMOS18; # Bank
LOC = J25 | IOSTANDARD=LVCMOS18; # Bank
LOC = J26 | IOSTANDARD=LVCMOS18; # Bank
LOC = M24 | IOSTANDARD=LVCMOS18; # Bank
LOC = L24 | IOSTANDARD=LVCMOS18; # Bank
LOC = K23 | IOSTANDARD=LVCMOS18; # Bank
LOC = J23 | IOSTANDARD=LVCMOS18; # Bank
LOC = M22 | IOSTANDARD=LVCMOS18; # Bank
LOC = L22 | IOSTANDARD=LVCMOS18; # Bank
LOC = L25 | IOSTANDARD=LVCMOS18; # Bank
LOC = L26 | IOSTANDARD=LVCMOS18; # Bank
LOC = K22 | IOSTANDARD=LVCMOS18; # Bank
LOC = J22 | IOSTANDARD=LVCMOS18; # Bank
LOC = M21 | IOSTANDARD=LVCMOS18; # Bank
LOC = L21 | IOSTANDARD=LVCMOS18; # Bank
LOC = P21 | IOSTANDARD=LVCMOS18; # Bank
LOC = N21 | IOSTANDARD=LVCMOS18; # Bank
LOC = P25 | IOSTANDARD=LVCMOS18; # Bank
LOC = P26 | IOSTANDARD=LVCMOS18; # Bank
LOC = P22 | IOSTANDARD=LVCMOS18; # Bank
LOC = P23 | IOSTANDARD=LVCMOS18; # Bank
LOC = N25 | IOSTANDARD=LVCMOS18; # Bank
LOC = N26 | IOSTANDARD=LVCMOS18; # Bank
LOC = N23 | IOSTANDARD=LVCMOS18; # Bank
LOC = N24 | IOSTANDARD=LVCMOS18; # Bank
LOC = M27 | IOSTANDARD=LVCMOS18; # Bank
LOC = L27 | IOSTANDARD=LVCMOS18; # Bank
LOC = M26 | IOSTANDARD=LVCMOS18; # Bank
LOC = F21 | IOSTANDARD=SSTL15; # Bank
LOC = A24 | IOSTANDARD=SSTL15; # Bank
LOC = A25 | IOSTANDARD=SSTL15; # Bank
LOC = B22 | IOSTANDARD=SSTL15; # Bank
LOC = A22 | IOSTANDARD=SSTL15; # Bank
LOC = A26 | IOSTANDARD=DIFF_SSTL15; # Bank
LOC = A27 | IOSTANDARD=DIFF_SSTL15; # Bank
LOC = C23 | IOSTANDARD=SSTL15; # Bank
LOC = B23 | IOSTANDARD=SSTL15; # Bank
LOC = B26 | IOSTANDARD=SSTL15; # Bank
LOC = B27 | IOSTANDARD=SSTL15; # Bank
LOC = C24 | IOSTANDARD=SSTL15; # Bank
LOC = B24 | IOSTANDARD=SSTL15; # Bank
LOC = E23 | IOSTANDARD=SSTL15; # Bank
LOC = E24 | IOSTANDARD=SSTL15; # Bank
LOC = F22 | IOSTANDARD=SSTL15; # Bank
LOC = E22 | IOSTANDARD=SSTL15; # Bank
LOC = F25 | IOSTANDARD=DIFF_SSTL15; # Bank
LOC = E25 | IOSTANDARD=DIFF_SSTL15; # Bank
LOC = D22 | IOSTANDARD=SSTL15; # Bank
LOC = D23 | IOSTANDARD=SSTL15; # Bank
LOC = D25 | IOSTANDARD=SSTL15; # Bank
LOC = D26 | IOSTANDARD=SSTL15; # Bank
LOC = C25 | IOSTANDARD=SSTL15; # Bank
LOC = C26 | IOSTANDARD=SSTL15; # Bank
LOC = D27 | IOSTANDARD=SSTL15; # Bank
LOC = D28 | IOSTANDARD=SSTL15; # Bank
LOC = C28 | IOSTANDARD=SSTL15; # Bank
LOC = C29 | IOSTANDARD=LVCMOS15; # Bank
LOC = B28 | IOSTANDARD=DIFF_SSTL15; # Bank
LOC = B29 | IOSTANDARD=DIFF_SSTL15; # Bank
LOC = A31 | IOSTANDARD=SSTL15; # Bank
LOC = A32 | IOSTANDARD=SSTL15; # Bank
LOC = A29 | IOSTANDARD=SSTL15; # Bank
LOC = A30 | IOSTANDARD=SSTL15; # Bank
LOC = C31 | IOSTANDARD=SSTL15; # Bank
LOC = B31 | IOSTANDARD=SSTL15; # Bank
LOC = E30 | IOSTANDARD=SSTL15; # Bank
LOC = D31 | IOSTANDARD=SSTL15; # Bank
LOC = D30 | IOSTANDARD=SSTL15; # Bank
LOC = C30 | IOSTANDARD=SSTL15; # Bank
LOC = E27 | IOSTANDARD=DIFF_SSTL15; # Bank
LOC = E28 | IOSTANDARD=DIFF_SSTL15; # Bank
LOC = F29 | IOSTANDARD=SSTL15; # Bank
LOC = E29 | IOSTANDARD=SSTL15; # Bank
LOC = F26 | IOSTANDARD=SSTL15; # Bank
LOC = F27 | IOSTANDARD=SSTL15; # Bank
LOC = F30 | IOSTANDARD=SSTL15; # Bank
LOC = F31 | IOSTANDARD=SSTL15; # Bank
LOC = F24 | IOSTANDARD=SSTL15; # Bank
LOC = K18 | IOSTANDARD=SSTL15; # Bank
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36 VCCO - FMC1_VIO_B_M2C - IO_L10N_T1_36
36 VCCO - FMC1_VIO_B_M2C - IO_L11P_T1_SRCC_36
36 VCCO - FMC1_VIO_B_M2C - IO_L11N_T1_SRCC_36
36 VCCO - FMC1_VIO_B_M2C - IO_L12P_T1_MRCC_36
36 VCCO - FMC1_VIO_B_M2C - IO_L12N_T1_MRCC_36
36 VCCO - FMC1_VIO_B_M2C - IO_L13P_T2_MRCC_36
36 VCCO - FMC1_VIO_B_M2C - IO_L13N_T2_MRCC_36
36 VCCO - FMC1_VIO_B_M2C - IO_L14P_T2_SRCC_36
36 VCCO - FMC1_VIO_B_M2C - IO_L14N_T2_SRCC_36
36 VCCO - FMC1_VIO_B_M2C - IO_L15P_T2_DQS_36
36 VCCO - FMC1_VIO_B_M2C - IO_L15N_T2_DQS_36
36 VCCO - FMC1_VIO_B_M2C - IO_L16P_T2_36
36 VCCO - FMC1_VIO_B_M2C - IO_L16N_T2_36
36 VCCO - FMC1_VIO_B_M2C - IO_L17P_T2_36
36 VCCO - FMC1_VIO_B_M2C - IO_L17N_T2_36
36 VCCO - FMC1_VIO_B_M2C - IO_L18P_T2_36
36 VCCO - FMC1_VIO_B_M2C - IO_L18N_T2_36
36 VCCO - FMC1_VIO_B_M2C - IO_L19P_T3_36
36 VCCO - FMC1_VIO_B_M2C - IO_L19N_T3_VREF_36
36 VCCO - FMC1_VIO_B_M2C - IO_L20P_T3_36
36 VCCO - FMC1_VIO_B_M2C - IO_L20N_T3_36
36 VCCO - FMC1_VIO_B_M2C - IO_L21P_T3_DQS_36
36 VCCO - FMC1_VIO_B_M2C - IO_L21N_T3_DQS_36
36 VCCO - FMC1_VIO_B_M2C - IO_L22P_T3_36
36 VCCO - FMC1_VIO_B_M2C - IO_L22N_T3_36
36 VCCO - FMC1_VIO_B_M2C - IO_L23P_T3_36
36 VCCO - FMC1_VIO_B_M2C - IO_L23N_T3_36
36 VCCO - FMC1_VIO_B_M2C - IO_L24P_T3_36
36 VCCO - FMC1_VIO_B_M2C - IO_L24N_T3_36
36 VCCO - FMC1_VIO_B_M2C - IO_25_VRP_36
37 VCCO - VCC1V5_FPGA - IO_0_VRN_37
37 VCCO - VCC1V5_FPGA - IO_L1P_T0_37
37 VCCO - VCC1V5_FPGA - IO_L1N_T0_37
37 VCCO - VCC1V5_FPGA - IO_L2P_T0_37
37 VCCO - VCC1V5_FPGA - IO_L2N_T0_37
37 VCCO - VCC1V5_FPGA - IO_L3P_T0_DQS_37
37 VCCO - VCC1V5_FPGA - IO_L3N_T0_DQS_37
37 VCCO - VCC1V5_FPGA - IO_L4P_T0_37
37 VCCO - VCC1V5_FPGA - IO_L4N_T0_37
37 VCCO - VCC1V5_FPGA - IO_L5P_T0_37
37 VCCO - VCC1V5_FPGA - IO_L5N_T0_37
37 VCCO - VCC1V5_FPGA - IO_L6P_T0_37
37 VCCO - VCC1V5_FPGA - IO_L6N_T0_VREF_37
37 VCCO - VCC1V5_FPGA - IO_L7P_T1_37
37 VCCO - VCC1V5_FPGA - IO_L7N_T1_37
37 VCCO - VCC1V5_FPGA - IO_L8P_T1_37
37 VCCO - VCC1V5_FPGA - IO_L8N_T1_37
37 VCCO - VCC1V5_FPGA - IO_L9P_T1_DQS_37
37 VCCO - VCC1V5_FPGA - IO_L9N_T1_DQS_37
37 VCCO - VCC1V5_FPGA - IO_L10P_T1_37
37 VCCO - VCC1V5_FPGA - IO_L10N_T1_37
37 VCCO - VCC1V5_FPGA - IO_L11P_T1_SRCC_37
37 VCCO - VCC1V5_FPGA - IO_L11N_T1_SRCC_37
37 VCCO - VCC1V5_FPGA - IO_L12P_T1_MRCC_37
37 VCCO - VCC1V5_FPGA - IO_L12N_T1_MRCC_37
37 VCCO - VCC1V5_FPGA - IO_L13P_T2_MRCC_37
37 VCCO - VCC1V5_FPGA - IO_L13N_T2_MRCC_37
37 VCCO - VCC1V5_FPGA - IO_L14P_T2_SRCC_37
37 VCCO - VCC1V5_FPGA - IO_L14N_T2_SRCC_37
37 VCCO - VCC1V5_FPGA - IO_L15P_T2_DQS_37
37 VCCO - VCC1V5_FPGA - IO_L15N_T2_DQS_37
37 VCCO - VCC1V5_FPGA - IO_L16P_T2_37
37 VCCO - VCC1V5_FPGA - IO_L16N_T2_37
37 VCCO - VCC1V5_FPGA - IO_L17P_T2_37
37 VCCO - VCC1V5_FPGA - IO_L17N_T2_37
37 VCCO - VCC1V5_FPGA - IO_L18P_T2_37
37 VCCO - VCC1V5_FPGA - IO_L18N_T2_37
37 VCCO - VCC1V5_FPGA - IO_L19P_T3_37
37 VCCO - VCC1V5_FPGA - IO_L19N_T3_VREF_37
37 VCCO - VCC1V5_FPGA - IO_L20P_T3_37
37 VCCO - VCC1V5_FPGA - IO_L20N_T3_37
37 VCCO - VCC1V5_FPGA - IO_L21P_T3_DQS_37
37 VCCO - VCC1V5_FPGA - IO_L21N_T3_DQS_37
37 VCCO - VCC1V5_FPGA - IO_L22P_T3_37
37 VCCO - VCC1V5_FPGA - IO_L22N_T3_37
37 VCCO - VCC1V5_FPGA - IO_L23P_T3_37
37 VCCO - VCC1V5_FPGA - IO_L23N_T3_37
37 VCCO - VCC1V5_FPGA - IO_L24P_T3_37
37 VCCO - VCC1V5_FPGA - IO_L24N_T3_37
37 VCCO - VCC1V5_FPGA - IO_25_VRP_37
38 VCCO - VCC1V5_FPGA - IO_0_VRN_38
VC707 Evaluation Board
UG885 (v1.2) February 1, 2013