Xilinx VC707 User Manual page 90

Appendix C: Master UCF Listing
NET DDR3_D15
NET DDR3_D8
NET DDR3_D9
NET DDR3_D12
NET DDR3_D13
NET DDR3_D7
#NET VTTVREF
NET DDR3_D3
NET DDR3_D2
NET DDR3_DQS0_P
NET DDR3_DQS0_N
NET DDR3_D1
NET DDR3_DM0
NET DDR3_D5
NET DDR3_D0
NET DDR3_D4
NET DDR3_D6
NET VRP_39
#NET 12N119
#NET GND
#NET 12N118
#NET GND
#NET 12N121
#NET GND
#NET 12N120
#NET 12N117
#NET GND
#NET 12N116
#NET 12N115
#NET 12N114
#NET 12N123
#NET GND
#NET 12N122
#NET GND
#NET 12N125
#NET GND
#NET 12N124
#NET GND
#NET 12N132
#NET GND
#NET 12N133
#NET GND
#NET 12N134
#NET GND
#NET 12N135
#NET 12N130
#NET GND
#NET 12N131
#NET 12N5
#NET 12N128
#NET 12N129
#NET 12N136
#NET GND
#NET 12N137
#NET GND
#NET 12N138
#NET GND
#NET 12N139
#NET GND
#NET 13N97
#NET 13N95
#NET 13N96
#NET 13N94
NET SFP_TX_P
NET SFP_RX_P
NET SFP_TX_N
NET SGMIICLK_Q0_P
NET SFP_RX_N
NET SGMIICLK_Q0_N
NET SMA_MGT_REFCLK_N
NET SMA_MGT_REFCLK_P
NET SGMII_TX_P
NET SGMII_RX_P
NET SGMII_TX_N
NET SGMII_RX_N
NET SMA_MGT_TX_P
NET SMA_MGT_RX_P
NET SMA_MGT_TX_N
NET SMA_MGT_RX_N
NET PCIE_TX4_P
NET PCIE_RX4_P
90
LOC = J15 | IOSTANDARD=SSTL15; # Bank
LOC = K14 | IOSTANDARD=SSTL15; # Bank
LOC = K13 | IOSTANDARD=SSTL15; # Bank
LOC = L16 | IOSTANDARD=SSTL15; # Bank
LOC = L15 | IOSTANDARD=SSTL15; # Bank
LOC = L12 | IOSTANDARD=SSTL15; # Bank
LOC = L11 | IOSTANDARD=SSTL15; # Bank
LOC = M14 | IOSTANDARD=SSTL15; # Bank
LOC = L14 | IOSTANDARD=SSTL15; # Bank
LOC = N16 | IOSTANDARD=SSTL15; # Bank
LOC = M16 | IOSTANDARD=SSTL15; # Bank
LOC = N13 | IOSTANDARD=SSTL15; # Bank
LOC = M13 | IOSTANDARD=SSTL15; # Bank
LOC = N15 | IOSTANDARD=SSTL15; # Bank
LOC = N14 | IOSTANDARD=SSTL15; # Bank
LOC = M12 | IOSTANDARD=SSTL15; # Bank
LOC = M11 | IOSTANDARD=SSTL15; # Bank
LOC = J11 | IOSTANDARD=SSTL15; # Bank
LOC = AW2
LOC = AW6
LOC = AW1
LOC = AW5
LOC = AY4
LOC = AY8
LOC = AY3
LOC = AW10
LOC = AY7
LOC = AW9
LOC = BA9
LOC = BA10
LOC = BA2
LOC = BA6
LOC = BA1
LOC = BA5
LOC = BB4
LOC = BB8
LOC = BB3
LOC = BB7
LOC = AR2
LOC = AP8
LOC = AR1
LOC = AP7
LOC = AT4
LOC = AR6
LOC = AT3
LOC = AT8
LOC = AR5
LOC = AT7
LOC = W9
LOC = AU9
LOC = AU10
LOC = AU2
LOC = AU6
LOC = AU1
LOC = AU5
LOC = AV4
LOC = AV8
LOC = AV3
LOC = AV7
LOC = AL2
LOC = AJ6
LOC = AL1
LOC = AJ5
LOC = AM4
LOC = AL6
LOC = AM3
LOC = AH8
LOC = AL5
LOC = AH7
LOC = AK7
LOC = AK8
LOC = AN2
LOC = AM8
LOC = AN1
LOC = AM7
LOC = AP4
LOC = AN6
LOC = AP3
LOC = AN5
LOC = AG2
LOC = AD4
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39 VCCO - VCC1V5_FPGA - IO_L16N_T2_39
39 VCCO - VCC1V5_FPGA - IO_L17P_T2_39
39 VCCO - VCC1V5_FPGA - IO_L17N_T2_39
39 VCCO - VCC1V5_FPGA - IO_L18P_T2_39
39 VCCO - VCC1V5_FPGA - IO_L18N_T2_39
39 VCCO - VCC1V5_FPGA - IO_L19P_T3_39
39 VCCO - VCC1V5_FPGA - IO_L19N_T3_VREF_39
39 VCCO - VCC1V5_FPGA - IO_L20P_T3_39
39 VCCO - VCC1V5_FPGA - IO_L20N_T3_39
39 VCCO - VCC1V5_FPGA - IO_L21P_T3_DQS_39
39 VCCO - VCC1V5_FPGA - IO_L21N_T3_DQS_39
39 VCCO - VCC1V5_FPGA - IO_L22P_T3_39
39 VCCO - VCC1V5_FPGA - IO_L22N_T3_39
39 VCCO - VCC1V5_FPGA - IO_L23P_T3_39
39 VCCO - VCC1V5_FPGA - IO_L23N_T3_39
39 VCCO - VCC1V5_FPGA - IO_L24P_T3_39
39 VCCO - VCC1V5_FPGA - IO_L24N_T3_39
39 VCCO - VCC1V5_FPGA - IO_25_VRP_39
; # Bank 111
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; # Bank 111
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; # Bank 111
; # Bank 111
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; # Bank 111
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; # Bank 113
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; # Bank 113
; # Bank 113
; # Bank 114
; # Bank 114
- MGTXTXP3_111
- MGTXRXP3_111
- MGTXTXN3_111
- MGTXRXN3_111
- MGTXTXP2_111
- MGTXRXP2_111
- MGTXTXN2_111
- MGTREFCLK0P_111
- MGTXRXN2_111
- MGTREFCLK0N_111
- MGTREFCLK1N_111
- MGTREFCLK1P_111
- MGTXTXP1_111
- MGTXRXP1_111
- MGTXTXN1_111
- MGTXRXN1_111
- MGTXTXP0_111
- MGTXRXP0_111
- MGTXTXN0_111
- MGTXRXN0_111
- MGTXTXP3_112
- MGTXRXP3_112
- MGTXTXN3_112
- MGTXRXN3_112
- MGTXTXP2_112
- MGTXRXP2_112
- MGTXTXN2_112
- MGTREFCLK0P_112
- MGTXRXN2_112
- MGTREFCLK0N_112
- MGTRREF_112
- MGTREFCLK1N_112
- MGTREFCLK1P_112
- MGTXTXP1_112
- MGTXRXP1_112
- MGTXTXN1_112
- MGTXRXN1_112
- MGTXTXP0_112
- MGTXRXP0_112
- MGTXTXN0_112
- MGTXRXN0_112
- MGTXTXP3_113
- MGTXRXP3_113
- MGTXTXN3_113
- MGTXRXN3_113
- MGTXTXP2_113
- MGTXRXP2_113
- MGTXTXN2_113
- MGTREFCLK0P_113
- MGTXRXN2_113
- MGTREFCLK0N_113
- MGTREFCLK1N_113
- MGTREFCLK1P_113
- MGTXTXP1_113
- MGTXRXP1_113
- MGTXTXN1_113
- MGTXRXN1_113
- MGTXTXP0_113
- MGTXRXP0_113
- MGTXTXN0_113
- MGTXRXN0_113
- MGTXTXP3_114
- MGTXRXP3_114
VC707 Evaluation Board
UG885 (v1.2) February 1, 2013