Xilinx VC707 User Manual page 10

Chapter 1: VC707 Evaluation Board Features
Each configuration interface corresponds to one or more configuration modes and bus
widths as listed in
4, and 5 respectively as shown in
X-Ref Target - Figure 1-3
The default mode setting is M[2:0] = 010, which selects Master BPI at board power-on. See
Configuration Options, page 71
Table 1-2: VC707 Board FPGA Configuration Modes
For full details on configuring the FPGA, see UG470, 7 Series FPGAs Configuration
User Guide.
I/O Voltage Rails
There are 17 I/O banks available on the Virtex-7 device. Sixteen I/O banks are available on
the VC707 board, bank 31 is not used. The voltages applied to the FPGA I/O banks used by
the VC707 board are listed in
Table 1-3: I/O Voltage Rails
10
Table 1-2. The mode switches M2, M1, and M0 are on SW11 positions 3,
ON Position = 1
Configuration SW13 DIP switch
Mode Settings (M[2:0])
Master BPI
JTAG
FPGA (U1) Power Supply Rail
Bank Net Name
Bank 0 VCC1V8_FPGA
Bank 13 VCC1V8_FPGA
Bank 14 VCC1V8_FPGA
Bank 15 VCC1V8_FPGA
(1)
Bank 16 VADJ_FPGA
(1)
Bank 17 VADJ_FPGA
(1)
Bank 18 VADJ_FPGA
(1)
Bank 19 VADJ_FPGA
Bank 31 NOT USED
Bank 33 VCC1V8_FPGA
Bank 34 VADJ_FPGA
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Figure 1-3.
1 2 3 4 5
Figure 1-3: SW11 Default Settings
for detailed information about the mode switch SW11.
010
101
Table 1-3.
Voltage
1.8V
1.8V
1.8V
1.8V
1.8V (default)
1.8V (default)
1.8V (default)
1.8V (default)
NA
1.8V
1.8V (default)
OFF Position = 0
UG885_c1_03_020612
Bus CCLK
Width Direction
x8, x16 Output
x1 Not Applicable
VC707 Evaluation Board
UG885 (v1.2) February 1, 2013