Configuration Options - Xilinx VC707 User Manual

X-Ref Target - Figure 1-35
XADC_VCC5V0
VADJ
Table 1-33
Table 1-33: XADC Header J19 Pinout
Net Name
VN, VP
XADC_VAUX0P, N
XADC_VAUX8N, P
DXP, DXN
XADC_AGND
XADC_VREF
XADC_VCC5V0
XADC_VCC_HEADER
VADJ
GND
XADC_GPIO_3, 2, 1, 0

Configuration Options

The FPGA on the VC707 board can be configured by the following methods:
•
•
See UG470, 7 Series FPGAs Configuration User Guide for further details on configuration
modes.
The method used to configure the FPGA is controlled by the mode pin (M2, M1, M0)
settings selected through DIP switch SW11.
settings.
VC707 Evaluation Board
UG885 (v1.2) February 1, 2013
XADC_VN
XADC_VAUX0P
XADC_VAUX8N
XADC_DXP
XADC_VREF
XADC_GPIO_1
XADC_GPIO_3
Figure 1-35: XADC Header (J19)
describes the XADC header J19 pin functions.
J19 Pin
Number
1, 2 Dedicated analog input channel for the XADC.
Auxiliary analog input channel 0. Also supports use as I/O inputs when
3, 6
anti-alias capacitor is not present.
Auxiliary analog input channel 8. Also supports use as I/O inputs when
7, 8
anti-alias capacitor is not present.
9, 12 Access to thermal diode.
4, 5, 10 Analog ground reference.
11 1.25V reference from the board.
13 Filtered 5V supply from board.
14 Analog 1.8V supply for XADC.
15 VCCO supply for bank which is the source of DIO pins.
16 Digital Ground (board) Reference
Digital I/O. These pins should come from the same bank. These I/Os should
19, 20, 17, 18 not be shared with other functions because they are required to support 3-state
operation.
Master BPI (uses the Linear BPI Flash).
JTAG (uses the USB-to-JTAG Bridge or Download cable). See
more information
www.xilinx.com
J19
1 2
3 4
5 6 XADC_VAUX0N
XADC_VAUX8P
7 8
9 10
11 12
XADC_VCC_HEADER
13 14
15 16
17 18 XADC_GPIO_0
XADC_GPIO_2
19 20
GND
XADC_AGND XADC_AGND
Description
Table 1-34 lists the supported mode switch
Configuration Options
XADC_VP
XADC_DXN
UG885_c1_32_030512
USB JTAG, page 22 for
71