Xilinx VC707 User Manual page 86

Appendix C: Master UCF Listing
NET HDMI_R_D4
NET HDMI_R_D3
NET HDMI_R_D2
NET HDMI_R_D1
NET HDMI_R_D0
NET HDMI_INT
NET HDMI_R_D17
NET HDMI_R_D16
NET HDMI_R_D15
NET HDMI_R_D14
NET HDMI_R_D13
NET HDMI_R_D12
NET HDMI_R_DE
NET HDMI_R_SPDIF
NET HDMI_SPDIF_OUT_LS
NET HDMI_R_VSYNC
NET HDMI_R_HSYNC
NET HDMI_R_CLK
NET HDMI_R_D35
NET HDMI_R_D34
NET HDMI_R_D33
NET HDMI_R_D32
NET HDMI_R_D31
NET HDMI_R_D30
NET HDMI_R_D29
NET HDMI_R_D28
NET HDMI_R_D27
NET HDMI_R_D26
NET HDMI_R_D25
NET HDMI_R_D24
NET HDMI_R_D23
NET HDMI_R_D22
NET HDMI_R_D21
NET HDMI_R_D20
NET HDMI_R_D19
NET HDMI_R_D18
#NET 7N1099
NET XADC_GPIO_0
NET XADC_GPIO_1
NET XADC_GPIO_2
NET XADC_GPIO_3
#NET VRP_33
#NET VRN_34
#NET 8N640
#NET 8N641
#NET 8N635
#NET 8N636
#NET 8N637
#NET 8N646
#NET 8N634
#NET 8N649
#NET 8N648
#NET 8N651
#NET 8N650
#NET 8N652
NET FMC1_HPC_LA25_P
NET FMC1_HPC_LA25_N
NET FMC1_HPC_LA26_P
NET FMC1_HPC_LA26_N
NET FMC1_HPC_LA28_P
NET FMC1_HPC_LA28_N
NET FMC1_HPC_LA27_P
NET FMC1_HPC_LA27_N
NET FMC1_HPC_LA18_CC_P
NET FMC1_HPC_LA18_CC_N
NET FMC1_HPC_LA17_CC_P
NET FMC1_HPC_LA17_CC_N
NET FMC1_HPC_CLK1_M2C_P
NET FMC1_HPC_CLK1_M2C_N
NET FMC1_HPC_LA23_P
NET FMC1_HPC_LA23_N
NET FMC1_HPC_LA31_P
NET FMC1_HPC_LA31_N
NET FMC1_HPC_LA22_P
NET FMC1_HPC_LA22_N
NET FMC1_HPC_LA21_P
NET FMC1_HPC_LA21_N
NET FMC1_HPC_LA24_P
NET FMC1_HPC_LA24_N
NET FMC1_HPC_LA33_P
NET FMC1_HPC_LA33_N
86
LOC = AM21 | IOSTANDARD=LVCMOS18; # Bank
LOC = AJ21 | IOSTANDARD=LVCMOS18; # Bank
LOC = AJ20 | IOSTANDARD=LVCMOS18; # Bank
LOC = AL22 | IOSTANDARD=LVCMOS18; # Bank
LOC = AM22 | IOSTANDARD=LVCMOS18; # Bank
LOC = AM24 | IOSTANDARD=LVCMOS18; # Bank
LOC = AN24 | IOSTANDARD=LVCMOS18; # Bank
LOC = AM23 | IOSTANDARD=LVCMOS18; # Bank
LOC = AN23 | IOSTANDARD=LVCMOS18; # Bank
LOC = AP23 | IOSTANDARD=LVCMOS18; # Bank
LOC = AP22 | IOSTANDARD=LVCMOS18; # Bank
LOC = AN21 | IOSTANDARD=LVCMOS18; # Bank
LOC = AP21 | IOSTANDARD=LVCMOS18; # Bank
LOC = AR23 | IOSTANDARD=LVCMOS18; # Bank
LOC = AR22 | IOSTANDARD=LVCMOS18; # Bank
LOC = AT22 | IOSTANDARD=LVCMOS18; # Bank
LOC = AU22 | IOSTANDARD=LVCMOS18; # Bank
LOC = AU23 | IOSTANDARD=LVCMOS18; # Bank
LOC = AV23 | IOSTANDARD=LVCMOS18; # Bank
LOC = AW23 | IOSTANDARD=LVCMOS18; # Bank
LOC = AW22 | IOSTANDARD=LVCMOS18; # Bank
LOC = AT21 | IOSTANDARD=LVCMOS18; # Bank
LOC = AU21 | IOSTANDARD=LVCMOS18; # Bank
LOC = AR24 | IOSTANDARD=LVCMOS18; # Bank
LOC = AT24 | IOSTANDARD=LVCMOS18; # Bank
LOC = AV21 | IOSTANDARD=LVCMOS18; # Bank
LOC = AW21 | IOSTANDARD=LVCMOS18; # Bank
LOC = AU24 | IOSTANDARD=LVCMOS18; # Bank
LOC = AV24 | IOSTANDARD=LVCMOS18; # Bank
LOC = AY23 | IOSTANDARD=LVCMOS18; # Bank
LOC = AY22 | IOSTANDARD=LVCMOS18; # Bank
LOC = AY25 | IOSTANDARD=LVCMOS18; # Bank
LOC = BA25 | IOSTANDARD=LVCMOS18; # Bank
LOC = BA22 | IOSTANDARD=LVCMOS18; # Bank
LOC = BB22 | IOSTANDARD=LVCMOS18; # Bank
LOC = AY24 | IOSTANDARD=LVCMOS18; # Bank
LOC = BA24 | IOSTANDARD=LVCMOS18; # Bank
LOC = BA21 | IOSTANDARD=LVCMOS18; # Bank
LOC = BB21 | IOSTANDARD=LVCMOS18; # Bank
LOC = BB24 | IOSTANDARD=LVCMOS18; # Bank
LOC = BB23 | IOSTANDARD=LVCMOS18; # Bank
LOC = AN20 | IOSTANDARD=LVCMOS18; # Bank
LOC = R29 | IOSTANDARD=LVCMOS18; # Bank
LOC = K35 | IOSTANDARD=LVCMOS18; # Bank
LOC = J35 | IOSTANDARD=LVCMOS18; # Bank
LOC = J32 | IOSTANDARD=LVCMOS18; # Bank
LOC = J33 | IOSTANDARD=LVCMOS18; # Bank
LOC = K33 | IOSTANDARD=LVCMOS18; # Bank
LOC = K34 | IOSTANDARD=LVCMOS18; # Bank
LOC = L34 | IOSTANDARD=LVCMOS18; # Bank
LOC = L35 | IOSTANDARD=LVCMOS18; # Bank
LOC = M33 | IOSTANDARD=LVCMOS18; # Bank
LOC = M34 | IOSTANDARD=LVCMOS18; # Bank
LOC = H34 | IOSTANDARD=LVCMOS18; # Bank
LOC = H35 | IOSTANDARD=LVCMOS18; # Bank
LOC = K29 | IOSTANDARD=LVCMOS18; # Bank
LOC = K30 | IOSTANDARD=LVCMOS18; # Bank
LOC = J30 | IOSTANDARD=LVCMOS18; # Bank
LOC = H30 | IOSTANDARD=LVCMOS18; # Bank
LOC = L29 | IOSTANDARD=LVCMOS18; # Bank
LOC = L30 | IOSTANDARD=LVCMOS18; # Bank
LOC = J31 | IOSTANDARD=LVCMOS18; # Bank
LOC = H31 | IOSTANDARD=LVCMOS18; # Bank
LOC = M32 | IOSTANDARD=LVCMOS18; # Bank
LOC = L32 | IOSTANDARD=LVCMOS18; # Bank
LOC = L31 | IOSTANDARD=LVCMOS18; # Bank
LOC = K32 | IOSTANDARD=LVCMOS18; # Bank
LOC = N30 | IOSTANDARD=LVCMOS18; # Bank
LOC = M31 | IOSTANDARD=LVCMOS18; # Bank
LOC = P30 | IOSTANDARD=LVCMOS18; # Bank
LOC = N31 | IOSTANDARD=LVCMOS18; # Bank
LOC = M28 | IOSTANDARD=LVCMOS18; # Bank
LOC = M29 | IOSTANDARD=LVCMOS18; # Bank
LOC = R28 | IOSTANDARD=LVCMOS18; # Bank
LOC = P28 | IOSTANDARD=LVCMOS18; # Bank
LOC = N28 | IOSTANDARD=LVCMOS18; # Bank
LOC = N29 | IOSTANDARD=LVCMOS18; # Bank
LOC = R30 | IOSTANDARD=LVCMOS18; # Bank
LOC = P31 | IOSTANDARD=LVCMOS18; # Bank
LOC = U31 | IOSTANDARD=LVCMOS18; # Bank
LOC = T31 | IOSTANDARD=LVCMOS18; # Bank
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33 VCCO - VCC1V8_FPGA - IO_L4N_T0_33
33 VCCO - VCC1V8_FPGA - IO_L5P_T0_33
33 VCCO - VCC1V8_FPGA - IO_L5N_T0_33
33 VCCO - VCC1V8_FPGA - IO_L6P_T0_33
33 VCCO - VCC1V8_FPGA - IO_L6N_T0_VREF_33
33 VCCO - VCC1V8_FPGA - IO_L7P_T1_33
33 VCCO - VCC1V8_FPGA - IO_L7N_T1_33
33 VCCO - VCC1V8_FPGA - IO_L8P_T1_33
33 VCCO - VCC1V8_FPGA - IO_L8N_T1_33
33 VCCO - VCC1V8_FPGA - IO_L9P_T1_DQS_33
33 VCCO - VCC1V8_FPGA - IO_L9N_T1_DQS_33
33 VCCO - VCC1V8_FPGA - IO_L10P_T1_33
33 VCCO - VCC1V8_FPGA - IO_L10N_T1_33
33 VCCO - VCC1V8_FPGA - IO_L11P_T1_SRCC_33
33 VCCO - VCC1V8_FPGA - IO_L11N_T1_SRCC_33
33 VCCO - VCC1V8_FPGA - IO_L12P_T1_MRCC_33
33 VCCO - VCC1V8_FPGA - IO_L12N_T1_MRCC_33
33 VCCO - VCC1V8_FPGA - IO_L13P_T2_MRCC_33
33 VCCO - VCC1V8_FPGA - IO_L13N_T2_MRCC_33
33 VCCO - VCC1V8_FPGA - IO_L14P_T2_SRCC_33
33 VCCO - VCC1V8_FPGA - IO_L14N_T2_SRCC_33
33 VCCO - VCC1V8_FPGA - IO_L15P_T2_DQS_33
33 VCCO - VCC1V8_FPGA - IO_L15N_T2_DQS_33
33 VCCO - VCC1V8_FPGA - IO_L16P_T2_33
33 VCCO - VCC1V8_FPGA - IO_L16N_T2_33
33 VCCO - VCC1V8_FPGA - IO_L17P_T2_33
33 VCCO - VCC1V8_FPGA - IO_L17N_T2_33
33 VCCO - VCC1V8_FPGA - IO_L18P_T2_33
33 VCCO - VCC1V8_FPGA - IO_L18N_T2_33
33 VCCO - VCC1V8_FPGA - IO_L19P_T3_33
33 VCCO - VCC1V8_FPGA - IO_L19N_T3_VREF_33
33 VCCO - VCC1V8_FPGA - IO_L20P_T3_33
33 VCCO - VCC1V8_FPGA - IO_L20N_T3_33
33 VCCO - VCC1V8_FPGA - IO_L21P_T3_DQS_33
33 VCCO - VCC1V8_FPGA - IO_L21N_T3_DQS_33
33 VCCO - VCC1V8_FPGA - IO_L22P_T3_33
33 VCCO - VCC1V8_FPGA - IO_L22N_T3_33
33 VCCO - VCC1V8_FPGA - IO_L23P_T3_33
33 VCCO - VCC1V8_FPGA - IO_L23N_T3_33
33 VCCO - VCC1V8_FPGA - IO_L24P_T3_33
33 VCCO - VCC1V8_FPGA - IO_L24N_T3_33
33 VCCO - VCC1V8_FPGA - IO_25_VRP_33
34 VCCO - VADJ_FPGA - IO_0_VRN_34
34 VCCO - VADJ_FPGA - IO_L1P_T0_34
34 VCCO - VADJ_FPGA - IO_L1N_T0_34
34 VCCO - VADJ_FPGA - IO_L2P_T0_34
34 VCCO - VADJ_FPGA - IO_L2N_T0_34
34 VCCO - VADJ_FPGA - IO_L3P_T0_DQS_34
34 VCCO - VADJ_FPGA - IO_L3N_T0_DQS_34
34 VCCO - VADJ_FPGA - IO_L4P_T0_34
34 VCCO - VADJ_FPGA - IO_L4N_T0_34
34 VCCO - VADJ_FPGA - IO_L5P_T0_34
34 VCCO - VADJ_FPGA - IO_L5N_T0_34
34 VCCO - VADJ_FPGA - IO_L6P_T0_34
34 VCCO - VADJ_FPGA - IO_L6N_T0_VREF_34
34 VCCO - VADJ_FPGA - IO_L7P_T1_34
34 VCCO - VADJ_FPGA - IO_L7N_T1_34
34 VCCO - VADJ_FPGA - IO_L8P_T1_34
34 VCCO - VADJ_FPGA - IO_L8N_T1_34
34 VCCO - VADJ_FPGA - IO_L9P_T1_DQS_34
34 VCCO - VADJ_FPGA - IO_L9N_T1_DQS_34
34 VCCO - VADJ_FPGA - IO_L10P_T1_34
34 VCCO - VADJ_FPGA - IO_L10N_T1_34
34 VCCO - VADJ_FPGA - IO_L11P_T1_SRCC_34
34 VCCO - VADJ_FPGA - IO_L11N_T1_SRCC_34
34 VCCO - VADJ_FPGA - IO_L12P_T1_MRCC_34
34 VCCO - VADJ_FPGA - IO_L12N_T1_MRCC_34
34 VCCO - VADJ_FPGA - IO_L13P_T2_MRCC_34
34 VCCO - VADJ_FPGA - IO_L13N_T2_MRCC_34
34 VCCO - VADJ_FPGA - IO_L14P_T2_SRCC_34
34 VCCO - VADJ_FPGA - IO_L14N_T2_SRCC_34
34 VCCO - VADJ_FPGA - IO_L15P_T2_DQS_34
34 VCCO - VADJ_FPGA - IO_L15N_T2_DQS_34
34 VCCO - VADJ_FPGA - IO_L16P_T2_34
34 VCCO - VADJ_FPGA - IO_L16N_T2_34
34 VCCO - VADJ_FPGA - IO_L17P_T2_34
34 VCCO - VADJ_FPGA - IO_L17N_T2_34
34 VCCO - VADJ_FPGA - IO_L18P_T2_34
34 VCCO - VADJ_FPGA - IO_L18N_T2_34
34 VCCO - VADJ_FPGA - IO_L19P_T3_34
34 VCCO - VADJ_FPGA - IO_L19N_T3_VREF_34
VC707 Evaluation Board
UG885 (v1.2) February 1, 2013