Xilinx VC707 User Manual page 72

Chapter 1: VC707 Evaluation Board Features
Table 1-34: Mode Switch SW11 Settings
Figure 1-36
X-Ref Target - Figure 1-36
FLASH_A25
FLASH_A24
FPGA_M2
FPGA_M1
FPGA_M0
The mode pins settings on SW11 determine if the Linear BPI Flash is used for configuring
the FPGA. DIP switch SW11 also provides the upper two address bits for the Linear BPI
Flash and can be used to select one of multiple stored configuration bitstreams.
shows the connectivity between the onboard nonvolatile Flash devices used for
configuration and the FPGA.
To obtain the fastest configuration speed an external 80 MHz oscillator is wired to the
EMCCLK pin of the FPGA. This allows users to create bitstreams that configure the FPGA
over the 16-bit datapath from the Linear BPI Flash memory at a maximum synchronous
read rate of 40 MHz. The bitstream stored in the flash memory must be generated with a
bitgen option to divide the EMCCLK by two.
72
Mode Pins
Configuration Mode
(M2, M1, M0)
010
101
shows mode switch SW13.
R396 R398
1.21kΩ 1.21kΩ
0.1 W 0.1 W
1% 1%
R397 R399
1.21kΩ 1.21kΩ
0.1 W 0.1 W
1% 1%
GND
Figure 1-36: Mode Switch
www.xilinx.com
Master BPI
JTAG
VCC2V5
SW11
ON
10 1
9 2
3
8
7 4
5
6
SDA05H1SBD
R400
1.21kΩ
0.1 W
1%
R401 R402
220Ω 220Ω
0.1 W 0.1 W
1% 1%
UG885_c1_33_030512
Figure 1-37
VC707 Evaluation Board
UG885 (v1.2) February 1, 2013