Xilinx VC707 User Manual page 85

NET FMC2_HPC_LA28_P
NET FMC2_HPC_LA28_N
NET FMC2_HPC_LA20_P
NET FMC2_HPC_LA20_N
NET FMC2_HPC_LA29_P
NET FMC2_HPC_LA29_N
NET FMC2_HPC_LA19_P
NET FMC2_HPC_LA19_N
NET FMC2_HPC_LA22_P
NET FMC2_HPC_LA22_N
NET FMC2_HPC_LA31_P
NET FMC2_HPC_LA31_N
#NET 6N1047
#NET 6N1048
#NET 6N1024
#NET 6N1025
#NET 6N1027
#NET 6N1026
#NET 6N1031
#NET 6N1030
#NET 6N1028
#NET 6N1029
#NET 6N1023
#NET VRN_19
#NET 6N957
#NET 6N958
#NET 6N959
#NET 6N960
#NET 6N961
#NET 6N963
#NET 6N962
#NET 6N964
#NET 6N967
#NET 6N968
#NET 6N969
#NET 6N970
NET FMC1_HPC_LA04_P
NET FMC1_HPC_LA04_N
NET FMC1_HPC_LA13_P
NET FMC1_HPC_LA13_N
NET FMC1_HPC_LA07_P
NET FMC1_HPC_LA07_N
NET FMC1_HPC_LA11_P
NET FMC1_HPC_LA11_N
NET FMC1_HPC_LA01_CC_P
NET FMC1_HPC_LA01_CC_N
NET FMC1_HPC_LA00_CC_P
NET FMC1_HPC_LA00_CC_N
NET FMC1_HPC_CLK0_M2C_P
NET FMC1_HPC_CLK0_M2C_N
NET FMC1_HPC_LA05_P
NET FMC1_HPC_LA05_N
NET FMC1_HPC_LA06_P
NET FMC1_HPC_LA06_N
NET FMC1_HPC_LA03_P
NET FMC1_HPC_LA03_N
NET FMC1_HPC_LA16_P
NET FMC1_HPC_LA16_N
NET FMC1_HPC_LA15_P
NET FMC1_HPC_LA15_N
NET FMC1_HPC_LA02_P
NET FMC1_HPC_LA02_N
NET FMC1_HPC_LA08_P
NET FMC1_HPC_LA08_N
NET FMC1_HPC_LA09_P
NET FMC1_HPC_LA09_N
NET FMC1_HPC_LA10_P
NET FMC1_HPC_LA10_N
NET FMC1_HPC_LA12_P
NET FMC1_HPC_LA12_N
NET FMC1_HPC_LA14_P
NET FMC1_HPC_LA14_N
#NET VRP_19
#NET VRN_33
NET HDMI_R_D11
NET HDMI_R_D10
NET HDMI_R_D9
NET HDMI_R_D8
NET HDMI_R_D7
NET HDMI_R_D6
NET HDMI_R_D5
VC707 Evaluation Board
UG885 (v1.2) February 1, 2013
LOC = V35 | IOSTANDARD=LVCMOS18; # Bank
LOC = V36 | IOSTANDARD=LVCMOS18; # Bank
LOC = V33 | IOSTANDARD=LVCMOS18; # Bank
LOC = V34 | IOSTANDARD=LVCMOS18; # Bank
LOC = W36 | IOSTANDARD=LVCMOS18; # Bank
LOC = W37 | IOSTANDARD=LVCMOS18; # Bank
LOC = U32 | IOSTANDARD=LVCMOS18; # Bank
LOC = U33 | IOSTANDARD=LVCMOS18; # Bank
LOC = W32 | IOSTANDARD=LVCMOS18; # Bank
LOC = W33 | IOSTANDARD=LVCMOS18; # Bank
LOC = V39 | IOSTANDARD=LVCMOS18; # Bank
LOC = V40 | IOSTANDARD=LVCMOS18; # Bank
LOC = T40 | IOSTANDARD=LVCMOS18; # Bank
LOC = T41 | IOSTANDARD=LVCMOS18; # Bank
LOC = W41 | IOSTANDARD=LVCMOS18; # Bank
LOC = W42 | IOSTANDARD=LVCMOS18; # Bank
LOC = U41 | IOSTANDARD=LVCMOS18; # Bank
LOC = T42 | IOSTANDARD=LVCMOS18; # Bank
LOC = W38 | IOSTANDARD=LVCMOS18; # Bank
LOC = V38 | IOSTANDARD=LVCMOS18; # Bank
LOC = V41 | IOSTANDARD=LVCMOS18; # Bank
LOC = U42 | IOSTANDARD=LVCMOS18; # Bank
LOC = W35 | IOSTANDARD=LVCMOS18; # Bank
LOC = L36 | IOSTANDARD=LVCMOS18; # Bank
LOC = E40 | IOSTANDARD=LVCMOS18; # Bank
LOC = D40 | IOSTANDARD=LVCMOS18; # Bank
LOC = A40 | IOSTANDARD=LVCMOS18; # Bank
LOC = A41 | IOSTANDARD=LVCMOS18; # Bank
LOC = D41 | IOSTANDARD=LVCMOS18; # Bank
LOC = D42 | IOSTANDARD=LVCMOS18; # Bank
LOC = B41 | IOSTANDARD=LVCMOS18; # Bank
LOC = B42 | IOSTANDARD=LVCMOS18; # Bank
LOC = F42 | IOSTANDARD=LVCMOS18; # Bank
LOC = E42 | IOSTANDARD=LVCMOS18; # Bank
LOC = C40 | IOSTANDARD=LVCMOS18; # Bank
LOC = C41 | IOSTANDARD=LVCMOS18; # Bank
LOC = H40 | IOSTANDARD=LVCMOS18; # Bank
LOC = H41 | IOSTANDARD=LVCMOS18; # Bank
LOC = H39 | IOSTANDARD=LVCMOS18; # Bank
LOC = G39 | IOSTANDARD=LVCMOS18; # Bank
LOC = G41 | IOSTANDARD=LVCMOS18; # Bank
LOC = G42 | IOSTANDARD=LVCMOS18; # Bank
LOC = F40 | IOSTANDARD=LVCMOS18; # Bank
LOC = F41 | IOSTANDARD=LVCMOS18; # Bank
LOC = J40 | IOSTANDARD=LVCMOS18; # Bank
LOC = J41 | IOSTANDARD=LVCMOS18; # Bank
LOC = K39 | IOSTANDARD=LVCMOS18; # Bank
LOC = K40 | IOSTANDARD=LVCMOS18; # Bank
LOC = L39 | IOSTANDARD=LVCMOS18; # Bank
LOC = L40 | IOSTANDARD=LVCMOS18; # Bank
LOC = M41 | IOSTANDARD=LVCMOS18; # Bank
LOC = L41 | IOSTANDARD=LVCMOS18; # Bank
LOC = K42 | IOSTANDARD=LVCMOS18; # Bank
LOC = J42 | IOSTANDARD=LVCMOS18; # Bank
LOC = M42 | IOSTANDARD=LVCMOS18; # Bank
LOC = L42 | IOSTANDARD=LVCMOS18; # Bank
LOC = K37 | IOSTANDARD=LVCMOS18; # Bank
LOC = K38 | IOSTANDARD=LVCMOS18; # Bank
LOC = M36 | IOSTANDARD=LVCMOS18; # Bank
LOC = L37 | IOSTANDARD=LVCMOS18; # Bank
LOC = P41 | IOSTANDARD=LVCMOS18; # Bank
LOC = N41 | IOSTANDARD=LVCMOS18; # Bank
LOC = M37 | IOSTANDARD=LVCMOS18; # Bank
LOC = M38 | IOSTANDARD=LVCMOS18; # Bank
LOC = R42 | IOSTANDARD=LVCMOS18; # Bank
LOC = P42 | IOSTANDARD=LVCMOS18; # Bank
LOC = N38 | IOSTANDARD=LVCMOS18; # Bank
LOC = M39 | IOSTANDARD=LVCMOS18; # Bank
LOC = R40 | IOSTANDARD=LVCMOS18; # Bank
LOC = P40 | IOSTANDARD=LVCMOS18; # Bank
LOC = N39 | IOSTANDARD=LVCMOS18; # Bank
LOC = N40 | IOSTANDARD=LVCMOS18; # Bank
LOC = N36 | IOSTANDARD=LVCMOS18; # Bank
LOC = AL24 | IOSTANDARD=LVCMOS18; # Bank
LOC = AJ23 | IOSTANDARD=LVCMOS18; # Bank
LOC = AK23 | IOSTANDARD=LVCMOS18; # Bank
LOC = AK20 | IOSTANDARD=LVCMOS18; # Bank
LOC = AL20 | IOSTANDARD=LVCMOS18; # Bank
LOC = AJ22 | IOSTANDARD=LVCMOS18; # Bank
LOC = AK22 | IOSTANDARD=LVCMOS18; # Bank
LOC = AL21 | IOSTANDARD=LVCMOS18; # Bank
www.xilinx.com
VC707 Board UCF Listing
18 VCCO - VADJ_FPGA - IO_L14P_T2_SRCC_18
18 VCCO - VADJ_FPGA - IO_L14N_T2_SRCC_18
18 VCCO - VADJ_FPGA - IO_L15P_T2_DQS_18
18 VCCO - VADJ_FPGA - IO_L15N_T2_DQS_18
18 VCCO - VADJ_FPGA - IO_L16P_T2_18
18 VCCO - VADJ_FPGA - IO_L16N_T2_18
18 VCCO - VADJ_FPGA - IO_L17P_T2_18
18 VCCO - VADJ_FPGA - IO_L17N_T2_18
18 VCCO - VADJ_FPGA - IO_L18P_T2_18
18 VCCO - VADJ_FPGA - IO_L18N_T2_18
18 VCCO - VADJ_FPGA - IO_L19P_T3_18
18 VCCO - VADJ_FPGA - IO_L19N_T3_VREF_18
18 VCCO - VADJ_FPGA - IO_L20P_T3_18
18 VCCO - VADJ_FPGA - IO_L20N_T3_18
18 VCCO - VADJ_FPGA - IO_L21P_T3_DQS_18
18 VCCO - VADJ_FPGA - IO_L21N_T3_DQS_18
18 VCCO - VADJ_FPGA - IO_L22P_T3_18
18 VCCO - VADJ_FPGA - IO_L22N_T3_18
18 VCCO - VADJ_FPGA - IO_L23P_T3_18
18 VCCO - VADJ_FPGA - IO_L23N_T3_18
18 VCCO - VADJ_FPGA - IO_L24P_T3_18
18 VCCO - VADJ_FPGA - IO_L24N_T3_18
18 VCCO - VADJ_FPGA - IO_25_VRP_18
19 VCCO - VADJ_FPGA - IO_0_VRN_19
19 VCCO - VADJ_FPGA - IO_L1P_T0_19
19 VCCO - VADJ_FPGA - IO_L1N_T0_19
19 VCCO - VADJ_FPGA - IO_L2P_T0_19
19 VCCO - VADJ_FPGA - IO_L2N_T0_19
19 VCCO - VADJ_FPGA - IO_L3P_T0_DQS_19
19 VCCO - VADJ_FPGA - IO_L3N_T0_DQS_19
19 VCCO - VADJ_FPGA - IO_L4P_T0_19
19 VCCO - VADJ_FPGA - IO_L4N_T0_19
19 VCCO - VADJ_FPGA - IO_L5P_T0_19
19 VCCO - VADJ_FPGA - IO_L5N_T0_19
19 VCCO - VADJ_FPGA - IO_L6P_T0_19
19 VCCO - VADJ_FPGA - IO_L6N_T0_VREF_19
19 VCCO - VADJ_FPGA - IO_L7P_T1_19
19 VCCO - VADJ_FPGA - IO_L7N_T1_19
19 VCCO - VADJ_FPGA - IO_L8P_T1_19
19 VCCO - VADJ_FPGA - IO_L8N_T1_19
19 VCCO - VADJ_FPGA - IO_L9P_T1_DQS_19
19 VCCO - VADJ_FPGA - IO_L9N_T1_DQS_19
19 VCCO - VADJ_FPGA - IO_L10P_T1_19
19 VCCO - VADJ_FPGA - IO_L10N_T1_19
19 VCCO - VADJ_FPGA - IO_L11P_T1_SRCC_19
19 VCCO - VADJ_FPGA - IO_L11N_T1_SRCC_19
19 VCCO - VADJ_FPGA - IO_L12P_T1_MRCC_19
19 VCCO - VADJ_FPGA - IO_L12N_T1_MRCC_19
19 VCCO - VADJ_FPGA - IO_L13P_T2_MRCC_19
19 VCCO - VADJ_FPGA - IO_L13N_T2_MRCC_19
19 VCCO - VADJ_FPGA - IO_L14P_T2_SRCC_19
19 VCCO - VADJ_FPGA - IO_L14N_T2_SRCC_19
19 VCCO - VADJ_FPGA - IO_L15P_T2_DQS_19
19 VCCO - VADJ_FPGA - IO_L15N_T2_DQS_19
19 VCCO - VADJ_FPGA - IO_L16P_T2_19
19 VCCO - VADJ_FPGA - IO_L16N_T2_19
19 VCCO - VADJ_FPGA - IO_L17P_T2_19
19 VCCO - VADJ_FPGA - IO_L17N_T2_19
19 VCCO - VADJ_FPGA - IO_L18P_T2_19
19 VCCO - VADJ_FPGA - IO_L18N_T2_19
19 VCCO - VADJ_FPGA - IO_L19P_T3_19
19 VCCO - VADJ_FPGA - IO_L19N_T3_VREF_19
19 VCCO - VADJ_FPGA - IO_L20P_T3_19
19 VCCO - VADJ_FPGA - IO_L20N_T3_19
19 VCCO - VADJ_FPGA - IO_L21P_T3_DQS_19
19 VCCO - VADJ_FPGA - IO_L21N_T3_DQS_19
19 VCCO - VADJ_FPGA - IO_L22P_T3_19
19 VCCO - VADJ_FPGA - IO_L22N_T3_19
19 VCCO - VADJ_FPGA - IO_L23P_T3_19
19 VCCO - VADJ_FPGA - IO_L23N_T3_19
19 VCCO - VADJ_FPGA - IO_L24P_T3_19
19 VCCO - VADJ_FPGA - IO_L24N_T3_19
19 VCCO - VADJ_FPGA - IO_25_VRP_19
33 VCCO - VCC1V8_FPGA - IO_0_VRN_33
33 VCCO - VCC1V8_FPGA - IO_L1P_T0_33
33 VCCO - VCC1V8_FPGA - IO_L1N_T0_33
33 VCCO - VCC1V8_FPGA - IO_L2P_T0_33
33 VCCO - VCC1V8_FPGA - IO_L2N_T0_33
33 VCCO - VCC1V8_FPGA - IO_L3P_T0_DQS_33
33 VCCO - VCC1V8_FPGA - IO_L3N_T0_DQS_33
33 VCCO - VCC1V8_FPGA - IO_L4P_T0_33
85