Xilinx VC707 User Manual page 82

Appendix C: Master UCF Listing
NET GPIO_DIP_SW7
NET GPIO_DIP_SW0
NET ROTARY_PUSH
NET SDIO_DAT0_LS
NET SDIO_CD_DAT3_LS
NET SDIO_DAT1_LS
NET SDIO_DAT2_LS
NET SDIO_CLK_LS
NET SDIO_CMD_LS
NET SDIO_SDDET
NET SDIO_SDWP
NET USER_SMA_GPIO_P
NET USER_SMA_GPIO_N
NET SFP_TX_DISABLE
NET ROTARY_INCA
NET ROTARY_INCB
NET FMC_VADJ_ON_B_LS
NET FLASH_D0
NET FLASH_D1
NET FLASH_D2
NET FLASH_D3
#NET 4N749
NET FPGA_EMCCLK
NET FLASH_D4
NET FLASH_D5
NET FLASH_D6
NET FLASH_D7
NET FLASH_CE_B
NET FLASH_D8
NET FLASH_D9
NET FLASH_D10
NET FLASH_D11
NET FLASH_D12
NET PHY_MDC_LS
NET FLASH_D13
NET FLASH_D14
NET FLASH_D15
NET PHY_RESET_LS
NET PHY_MDIO_LS
NET USER_CLOCK_P
NET USER_CLOCK_N
NET USER_SMA_CLOCK_P
NET USER_SMA_CLOCK_N
NET PHY_INT_LS
NET FMC_C2M_PG_LS
NET FLASH_WAIT
NET FMC1_HPC_PG_M2C_LS
NET FMC1_HPC_PRSNT_M2C_B_LS
NET FLASH_A15
NET FLASH_A14
NET FLASH_A13
NET FLASH_A12
NET FLASH_A11
NET FLASH_A10
NET FLASH_A9
NET FLASH_A8
NET FLASH_A7
NET FMC2_HPC_PG_M2C_LS
NET FLASH_A6
NET FLASH_A5
NET FLASH_A4
NET FLASH_A3
NET FLASH_A2
NET FLASH_A1
NET FLASH_A0
NET FMC2_HPC_PRSNT_M2C_B_LS
#NET VRN_15
NET XADC_VAUX0P_R
NET XADC_VAUX0N_R
NET XADC_VAUX8P_R
NET XADC_VAUX8N_R
NET LCD_DB5_LS
NET LCD_DB6_LS
NET LCD_DB7_LS
NET LCD_RS_LS
NET GPIO_LED_2_LS
NET GPIO_LED_3_LS
NET GPIO_LED_0_LS
NET GPIO_LED_1_LS
NET GPIO_SW_S
NET GPIO_SW_N
82
LOC = BB31 | IOSTANDARD=LVCMOS18; # Bank
LOC = AV30 | IOSTANDARD=LVCMOS18; # Bank
LOC = AW31 | IOSTANDARD=LVCMOS18; # Bank
LOC = AR30 | IOSTANDARD=LVCMOS18; # Bank
LOC = AT30 | IOSTANDARD=LVCMOS18; # Bank
LOC = AU31 | IOSTANDARD=LVCMOS18; # Bank
LOC = AV31 | IOSTANDARD=LVCMOS18; # Bank
LOC = AN30 | IOSTANDARD=LVCMOS18; # Bank
LOC = AP30 | IOSTANDARD=LVCMOS18; # Bank
LOC = AP32 | IOSTANDARD=LVCMOS18; # Bank
LOC = AR32 | IOSTANDARD=LVCMOS18; # Bank
LOC = AN31 | IOSTANDARD=LVCMOS18; # Bank
LOC = AP31 | IOSTANDARD=LVCMOS18; # Bank
LOC = AP33 | IOSTANDARD=LVCMOS18; # Bank
LOC = AR33 | IOSTANDARD=LVCMOS18; # Bank
LOC = AT31 | IOSTANDARD=LVCMOS18; # Bank
LOC = AH35 | IOSTANDARD=LVCMOS18; # Bank
LOC = AM36 | IOSTANDARD=LVCMOS18; # Bank
LOC = AN36 | IOSTANDARD=LVCMOS18; # Bank
LOC = AJ36 | IOSTANDARD=LVCMOS18; # Bank
LOC = AJ37 | IOSTANDARD=LVCMOS18; # Bank
LOC = AP36 | IOSTANDARD=LVCMOS18; # Bank
LOC = AP37 | IOSTANDARD=LVCMOS18; # Bank
LOC = AK37 | IOSTANDARD=LVCMOS18; # Bank
LOC = AL37 | IOSTANDARD=LVCMOS18; # Bank
LOC = AN35 | IOSTANDARD=LVCMOS18; # Bank
LOC = AP35 | IOSTANDARD=LVCMOS18; # Bank
LOC = AL36 | IOSTANDARD=LVCMOS18; # Bank
LOC = AM37 | IOSTANDARD=LVCMOS18; # Bank
LOC = AG33 | IOSTANDARD=LVCMOS18; # Bank
LOC = AH33 | IOSTANDARD=LVCMOS18; # Bank
LOC = AK35 | IOSTANDARD=LVCMOS18; # Bank
LOC = AL35 | IOSTANDARD=LVCMOS18; # Bank
LOC = AH31 | IOSTANDARD=LVCMOS18; # Bank
LOC = AJ31 | IOSTANDARD=LVCMOS18; # Bank
LOC = AH34 | IOSTANDARD=LVCMOS18; # Bank
LOC = AJ35 | IOSTANDARD=LVCMOS18; # Bank
LOC = AJ33 | IOSTANDARD=LVCMOS18; # Bank
LOC = AK33 | IOSTANDARD=LVCMOS18; # Bank
LOC = AK34 | IOSTANDARD=LVDS; # Bank
LOC = AL34 | IOSTANDARD=LVDS; # Bank
LOC = AJ32 | IOSTANDARD=LVCMOS18; # Bank
LOC = AK32 | IOSTANDARD=LVCMOS18; # Bank
LOC = AL31 | IOSTANDARD=LVCMOS18; # Bank
LOC = AL32 | IOSTANDARD=LVCMOS18; # Bank
LOC = AM34 | IOSTANDARD=LVCMOS18; # Bank
LOC = AN34 | IOSTANDARD=LVCMOS18; # Bank
LOC = AM31 | IOSTANDARD=LVCMOS18; # Bank
LOC = AM32 | IOSTANDARD=LVCMOS18; # Bank
LOC = AM33 | IOSTANDARD=LVCMOS18; # Bank
LOC = AN33 | IOSTANDARD=LVCMOS18; # Bank
LOC = AL29 | IOSTANDARD=LVCMOS18; # Bank
LOC = AL30 | IOSTANDARD=LVCMOS18; # Bank
LOC = AH29 | IOSTANDARD=LVCMOS18; # Bank
LOC = AH30 | IOSTANDARD=LVCMOS18; # Bank
LOC = AJ30 | IOSTANDARD=LVCMOS18; # Bank
LOC = AK30 | IOSTANDARD=LVCMOS18; # Bank
LOC = AF29 | IOSTANDARD=LVCMOS18; # Bank
LOC = AG29 | IOSTANDARD=LVCMOS18; # Bank
LOC = AK28 | IOSTANDARD=LVCMOS18; # Bank
LOC = AK29 | IOSTANDARD=LVCMOS18; # Bank
LOC = AF30 | IOSTANDARD=LVCMOS18; # Bank
LOC = AG31 | IOSTANDARD=LVCMOS18; # Bank
LOC = AH28 | IOSTANDARD=LVCMOS18; # Bank
LOC = AJ28 | IOSTANDARD=LVCMOS18; # Bank
LOC = AG32 | IOSTANDARD=LVCMOS18; # Bank
LOC = AM38 | IOSTANDARD=LVCMOS18; # Bank
LOC = AN38 | IOSTANDARD=LVCMOS18; # Bank
LOC = AP38 | IOSTANDARD=LVCMOS18; # Bank
LOC = AM41 | IOSTANDARD=LVCMOS18; # Bank
LOC = AM42 | IOSTANDARD=LVCMOS18; # Bank
LOC = AR38 | IOSTANDARD=LVCMOS18; # Bank
LOC = AR39 | IOSTANDARD=LVCMOS18; # Bank
LOC = AN40 | IOSTANDARD=LVCMOS18; # Bank
LOC = AN41 | IOSTANDARD=LVCMOS18; # Bank
LOC = AR37 | IOSTANDARD=LVCMOS18; # Bank
LOC = AT37 | IOSTANDARD=LVCMOS18; # Bank
LOC = AM39 | IOSTANDARD=LVCMOS18; # Bank
LOC = AN39 | IOSTANDARD=LVCMOS18; # Bank
LOC = AP40 | IOSTANDARD=LVCMOS18; # Bank
LOC = AR40 | IOSTANDARD=LVCMOS18; # Bank
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13 VCCO - VCC1V8_FPGA - IO_L17N_T2_13
13 VCCO - VCC1V8_FPGA - IO_L18P_T2_13
13 VCCO - VCC1V8_FPGA - IO_L18N_T2_13
13 VCCO - VCC1V8_FPGA - IO_L19P_T3_13
13 VCCO - VCC1V8_FPGA - IO_L19N_T3_VREF_13
13 VCCO - VCC1V8_FPGA - IO_L20P_T3_13
13 VCCO - VCC1V8_FPGA - IO_L20N_T3_13
13 VCCO - VCC1V8_FPGA - IO_L21P_T3_DQS_13
13 VCCO - VCC1V8_FPGA - IO_L21N_T3_DQS_13
13 VCCO - VCC1V8_FPGA - IO_L22P_T3_13
13 VCCO - VCC1V8_FPGA - IO_L22N_T3_13
13 VCCO - VCC1V8_FPGA - IO_L23P_T3_13
13 VCCO - VCC1V8_FPGA - IO_L23N_T3_13
13 VCCO - VCC1V8_FPGA - IO_L24P_T3_13
13 VCCO - VCC1V8_FPGA - IO_L24N_T3_13
13 VCCO - VCC1V8_FPGA - IO_25_VRP_13
14 VCCO - VCC1V8_FPGA - IO_0_VRN_14
14 VCCO - VCC1V8_FPGA - IO_L1P_T0_D00_MOSI_14
14 VCCO - VCC1V8_FPGA - IO_L1N_T0_D01_DIN_14
14 VCCO - VCC1V8_FPGA - IO_L2P_T0_D02_14
14 VCCO - VCC1V8_FPGA - IO_L2N_T0_D03_14
14 VCCO - VCC1V8_FPGA - IO_L3P_T0_DQS_PUDC_B_14
14 VCCO - VCC1V8_FPGA - IO_L3N_T0_DQS_EMCCLK_14
14 VCCO - VCC1V8_FPGA - IO_L4P_T0_D04_14
14 VCCO - VCC1V8_FPGA - IO_L4N_T0_D05_14
14 VCCO - VCC1V8_FPGA - IO_L5P_T0_D06_14
14 VCCO - VCC1V8_FPGA - IO_L5N_T0_D07_14
14 VCCO - VCC1V8_FPGA - IO_L6P_T0_FCS_B_14
14 VCCO - VCC1V8_FPGA - IO_L6N_T0_D08_VREF_14
14 VCCO - VCC1V8_FPGA - IO_L7P_T1_D09_14
14 VCCO - VCC1V8_FPGA - IO_L7N_T1_D10_14
14 VCCO - VCC1V8_FPGA - IO_L8P_T1_D11_14
14 VCCO - VCC1V8_FPGA - IO_L8N_T1_D12_14
14 VCCO - VCC1V8_FPGA - IO_L9P_T1_DQS_14
14 VCCO - VCC1V8_FPGA - IO_L9N_T1_DQS_D13_14
14 VCCO - VCC1V8_FPGA - IO_L10P_T1_D14_14
14 VCCO - VCC1V8_FPGA - IO_L10N_T1_D15_14
14 VCCO - VCC1V8_FPGA - IO_L11P_T1_SRCC_14
14 VCCO - VCC1V8_FPGA - IO_L11N_T1_SRCC_14
14 VCCO - VCC1V8_FPGA - IO_L12P_T1_MRCC_14
14 VCCO - VCC1V8_FPGA - IO_L12N_T1_MRCC_14
14 VCCO - VCC1V8_FPGA - IO_L13P_T2_MRCC_14
14 VCCO - VCC1V8_FPGA - IO_L13N_T2_MRCC_14
14 VCCO - VCC1V8_FPGA - IO_L14P_T2_SRCC_14
14 VCCO - VCC1V8_FPGA - IO_L14N_T2_SRCC_14
14 VCCO - VCC1V8_FPGA - IO_L15P_T2_DQS_RDWR_B_14
14 VCCO - VCC1V8_FPGA - IO_L15N_T2_DQS_DOUT_CSO_B_14
14 VCCO - VCC1V8_FPGA - IO_L16P_T2_CSI_B_14
14 VCCO - VCC1V8_FPGA - IO_L16N_T2_A15_D31_14
14 VCCO - VCC1V8_FPGA - IO_L17P_T2_A14_D30_14
14 VCCO - VCC1V8_FPGA - IO_L17N_T2_A13_D29_14
14 VCCO - VCC1V8_FPGA - IO_L18P_T2_A12_D28_14
14 VCCO - VCC1V8_FPGA - IO_L18N_T2_A11_D27_14
14 VCCO - VCC1V8_FPGA - IO_L19P_T3_A10_D26_14
14 VCCO - VCC1V8_FPGA - IO_L19N_T3_A09_D25_VREF_14
14 VCCO - VCC1V8_FPGA - IO_L20P_T3_A08_D24_14
14 VCCO - VCC1V8_FPGA - IO_L20N_T3_A07_D23_14
14 VCCO - VCC1V8_FPGA - IO_L21P_T3_DQS_14
14 VCCO - VCC1V8_FPGA - IO_L21N_T3_DQS_A06_D22_14
14 VCCO - VCC1V8_FPGA - IO_L22P_T3_A05_D21_14
14 VCCO - VCC1V8_FPGA - IO_L22N_T3_A04_D20_14
14 VCCO - VCC1V8_FPGA - IO_L23P_T3_A03_D19_14
14 VCCO - VCC1V8_FPGA - IO_L23N_T3_A02_D18_14
14 VCCO - VCC1V8_FPGA - IO_L24P_T3_A01_D17_14
14 VCCO - VCC1V8_FPGA - IO_L24N_T3_A00_D16_14
14 VCCO - VCC1V8_FPGA - IO_25_VRP_14
15 VCCO - VCC1V8_FPGA - IO_0_VRN_15
15 VCCO - VCC1V8_FPGA - IO_L1P_T0_AD0P_15
15 VCCO - VCC1V8_FPGA - IO_L1N_T0_AD0N_15
15 VCCO - VCC1V8_FPGA - IO_L2P_T0_AD8P_15
15 VCCO - VCC1V8_FPGA - IO_L2N_T0_AD8N_15
15 VCCO - VCC1V8_FPGA - IO_L3P_T0_DQS_AD1P_15
15 VCCO - VCC1V8_FPGA - IO_L3N_T0_DQS_AD1N_15
15 VCCO - VCC1V8_FPGA - IO_L4P_T0_15
15 VCCO - VCC1V8_FPGA - IO_L4N_T0_15
15 VCCO - VCC1V8_FPGA - IO_L5P_T0_AD9P_15
15 VCCO - VCC1V8_FPGA - IO_L5N_T0_AD9N_15
15 VCCO - VCC1V8_FPGA - IO_L6P_T0_15
15 VCCO - VCC1V8_FPGA - IO_L6N_T0_VREF_15
15 VCCO - VCC1V8_FPGA - IO_L7P_T1_AD2P_15
15 VCCO - VCC1V8_FPGA - IO_L7N_T1_AD2N_15
UG885 (v1.2) February 1, 2013
VC707 Evaluation Board