Xilinx VC707 User Manual page 89

NET DDR3_A9
NET DDR3_A1
NET DDR3_A5
NET DDR3_A12
NET DDR3_A0
NET DDR3_A3
NET DDR3_A11
NET DDR3_A4
NET DDR3_A10
NET DDR3_A13
NET DDR3_A7
NET VTTVREF
NET DDR3_A6
NET DDR3_A2
NET DDR3_A14
NET DDR3_A15
NET DDR3_BA0
NET DDR3_BA1
NET DDR3_BA2
NET DDR3_A8
NET DDR3_CLK1_P
NET DDR3_CLK1_N
NET SYSCLK_P
NET SYSCLK_N
NET DDR3_CLK0_P
NET DDR3_CLK0_N
NET DDR3_CKE0
NET DDR3_CKE1
NET DDR3_WE_B
NET DDR3_RAS_B
NET DDR3_CAS_B
NET DDR3_S0_B
NET DDR3_S1_B
NET DDR3_ODT0
NET DDR3_ODT1
NET DDR3_TEMP_EVENT
#NET 10N481
#NET VTTVREF
NET 10N483
NET 10N484
NET 10N485
NET 10N486
NET 10N487
NET 10N488
NET 10N489
NET 10N490
NET 10N491
NET 10N492
#NET VRP_38
#NET VRN_39
NET DDR3_D30
NET DDR3_D26
NET DDR3_D24
NET DDR3_DM3
NET DDR3_DQS3_P
NET DDR3_DQS3_N
NET DDR3_D28
NET DDR3_D25
NET DDR3_D31
NET DDR3_D27
NET DDR3_D29
#NET VTTVREF
#NET 10N563
NET DDR3_D16
NET DDR3_D19
NET DDR3_D17
NET DDR3_DQS2_P
NET DDR3_DQS2_N
NET DDR3_D21
NET DDR3_DM2
NET DDR3_D18
NET DDR3_D22
NET DDR3_D23
NET DDR3_D20
#NET 10N497
NET DDR3_D14
NET DDR3_D11
NET DDR3_D10
NET DDR3_DQS1_P
NET DDR3_DQS1_N
NET DDR3_DM1
VC707 Evaluation Board
UG885 (v1.2) February 1, 2013
LOC = C19 | IOSTANDARD=SSTL15; # Bank
LOC = B19 | IOSTANDARD=SSTL15; # Bank
LOC = A16 | IOSTANDARD=SSTL15; # Bank
LOC = A15 | IOSTANDARD=SSTL15; # Bank
LOC = A20 | IOSTANDARD=SSTL15; # Bank
LOC = A19 | IOSTANDARD=SSTL15; # Bank
LOC = B17 | IOSTANDARD=SSTL15; # Bank
LOC = A17 | IOSTANDARD=SSTL15; # Bank
LOC = B21 | IOSTANDARD=SSTL15; # Bank
LOC = A21 | IOSTANDARD=SSTL15; # Bank
LOC = C18 | IOSTANDARD=SSTL15; # Bank
LOC = B18 | IOSTANDARD=SSTL15; # Bank
LOC = D20 | IOSTANDARD=SSTL15; # Bank
LOC = C20 | IOSTANDARD=SSTL15; # Bank
LOC = F17 | IOSTANDARD=SSTL15; # Bank
LOC = E17 | IOSTANDARD=SSTL15; # Bank
LOC = D21 | IOSTANDARD=SSTL15; # Bank
LOC = C21 | IOSTANDARD=SSTL15; # Bank
LOC = D18 | IOSTANDARD=SSTL15; # Bank
LOC = D17 | IOSTANDARD=SSTL15; # Bank
LOC = G19 | IOSTANDARD=DIFF_SSTL15; # Bank
LOC = F19 | IOSTANDARD=DIFF_SSTL15; # Bank
LOC = E19 | IOSTANDARD=LVDS; # Bank
LOC = E18 | IOSTANDARD=LVDS; # Bank
LOC = H19 | IOSTANDARD=DIFF_SSTL15; # Bank
LOC = G18 | IOSTANDARD=DIFF_SSTL15; # Bank
LOC = K19 | IOSTANDARD=SSTL15; # Bank
LOC = J18 | IOSTANDARD=SSTL15; # Bank
LOC = F20 | IOSTANDARD=SSTL15; # Bank
LOC = E20 | IOSTANDARD=SSTL15; # Bank
LOC = K17 | IOSTANDARD=SSTL15; # Bank
LOC = J17 | IOSTANDARD=SSTL15; # Bank
LOC = J20 | IOSTANDARD=SSTL15; # Bank
LOC = H20 | IOSTANDARD=SSTL15; # Bank
LOC = H18 | IOSTANDARD=SSTL15; # Bank
LOC = G17 | IOSTANDARD=SSTL15; # Bank
LOC = P18 | IOSTANDARD=SSTL15; # Bank
LOC = P17 | IOSTANDARD=SSTL15; # Bank
LOC = M17 | IOSTANDARD=SSTL15; # Bank
LOC = L17 | IOSTANDARD=SSTL15; # Bank
LOC = N19 | IOSTANDARD=SSTL15; # Bank
LOC = N18 | IOSTANDARD=SSTL15; # Bank
LOC = M19 | IOSTANDARD=SSTL15; # Bank
LOC = M18 | IOSTANDARD=SSTL15; # Bank
LOC = P20 | IOSTANDARD=SSTL15; # Bank
LOC = N20 | IOSTANDARD=SSTL15; # Bank
LOC = L20 | IOSTANDARD=SSTL15; # Bank
LOC = L19 | IOSTANDARD=SSTL15; # Bank
LOC = K20 | IOSTANDARD=SSTL15; # Bank
LOC = J16 | IOSTANDARD=SSTL15; # Bank
LOC = C16 | IOSTANDARD=SSTL15; # Bank
LOC = B16 | IOSTANDARD=SSTL15; # Bank
LOC = B14 | IOSTANDARD=SSTL15; # Bank
LOC = A14 | IOSTANDARD=SSTL15; # Bank
LOC = C15 | IOSTANDARD=SSTL15; # Bank
LOC = C14 | IOSTANDARD=SSTL15; # Bank
LOC = D13 | IOSTANDARD=SSTL15; # Bank
LOC = C13 | IOSTANDARD=SSTL15; # Bank
LOC = D16 | IOSTANDARD=SSTL15; # Bank
LOC = D15 | IOSTANDARD=SSTL15; # Bank
LOC = E12 | IOSTANDARD=SSTL15; # Bank
LOC = D12 | IOSTANDARD=SSTL15; # Bank
LOC = F16 | IOSTANDARD=SSTL15; # Bank
LOC = E15 | IOSTANDARD=SSTL15; # Bank
LOC = E14 | IOSTANDARD=SSTL15; # Bank
LOC = E13 | IOSTANDARD=SSTL15; # Bank
LOC = H16 | IOSTANDARD=SSTL15; # Bank
LOC = G16 | IOSTANDARD=SSTL15; # Bank
LOC = G12 | IOSTANDARD=SSTL15; # Bank
LOC = F12 | IOSTANDARD=SSTL15; # Bank
LOC = F15 | IOSTANDARD=SSTL15; # Bank
LOC = F14 | IOSTANDARD=SSTL15; # Bank
LOC = G14 | IOSTANDARD=SSTL15; # Bank
LOC = G13 | IOSTANDARD=SSTL15; # Bank
LOC = H15 | IOSTANDARD=SSTL15; # Bank
LOC = H14 | IOSTANDARD=SSTL15; # Bank
LOC = J13 | IOSTANDARD=SSTL15; # Bank
LOC = H13 | IOSTANDARD=SSTL15; # Bank
LOC = K12 | IOSTANDARD=SSTL15; # Bank
LOC = J12 | IOSTANDARD=SSTL15; # Bank
LOC = K15 | IOSTANDARD=SSTL15; # Bank
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VC707 Board UCF Listing
38 VCCO - VCC1V5_FPGA - IO_L1P_T0_38
38 VCCO - VCC1V5_FPGA - IO_L1N_T0_38
38 VCCO - VCC1V5_FPGA - IO_L2P_T0_38
38 VCCO - VCC1V5_FPGA - IO_L2N_T0_38
38 VCCO - VCC1V5_FPGA - IO_L3P_T0_DQS_38
38 VCCO - VCC1V5_FPGA - IO_L3N_T0_DQS_38
38 VCCO - VCC1V5_FPGA - IO_L4P_T0_38
38 VCCO - VCC1V5_FPGA - IO_L4N_T0_38
38 VCCO - VCC1V5_FPGA - IO_L5P_T0_38
38 VCCO - VCC1V5_FPGA - IO_L5N_T0_38
38 VCCO - VCC1V5_FPGA - IO_L6P_T0_38
38 VCCO - VCC1V5_FPGA - IO_L6N_T0_VREF_38
38 VCCO - VCC1V5_FPGA - IO_L7P_T1_38
38 VCCO - VCC1V5_FPGA - IO_L7N_T1_38
38 VCCO - VCC1V5_FPGA - IO_L8P_T1_38
38 VCCO - VCC1V5_FPGA - IO_L8N_T1_38
38 VCCO - VCC1V5_FPGA - IO_L9P_T1_DQS_38
38 VCCO - VCC1V5_FPGA - IO_L9N_T1_DQS_38
38 VCCO - VCC1V5_FPGA - IO_L10P_T1_38
38 VCCO - VCC1V5_FPGA - IO_L10N_T1_38
38 VCCO - VCC1V5_FPGA - IO_L11P_T1_SRCC_38
38 VCCO - VCC1V5_FPGA - IO_L11N_T1_SRCC_38
38 VCCO - VCC1V5_FPGA - IO_L12P_T1_MRCC_38
38 VCCO - VCC1V5_FPGA - IO_L12N_T1_MRCC_38
38 VCCO - VCC1V5_FPGA - IO_L13P_T2_MRCC_38
38 VCCO - VCC1V5_FPGA - IO_L13N_T2_MRCC_38
38 VCCO - VCC1V5_FPGA - IO_L14P_T2_SRCC_38
38 VCCO - VCC1V5_FPGA - IO_L14N_T2_SRCC_38
38 VCCO - VCC1V5_FPGA - IO_L15P_T2_DQS_38
38 VCCO - VCC1V5_FPGA - IO_L15N_T2_DQS_38
38 VCCO - VCC1V5_FPGA - IO_L16P_T2_38
38 VCCO - VCC1V5_FPGA - IO_L16N_T2_38
38 VCCO - VCC1V5_FPGA - IO_L17P_T2_38
38 VCCO - VCC1V5_FPGA - IO_L17N_T2_38
38 VCCO - VCC1V5_FPGA - IO_L18P_T2_38
38 VCCO - VCC1V5_FPGA - IO_L18N_T2_38
38 VCCO - VCC1V5_FPGA - IO_L19P_T3_38
38 VCCO - VCC1V5_FPGA - IO_L19N_T3_VREF_38
38 VCCO - VCC1V5_FPGA - IO_L20P_T3_38
38 VCCO - VCC1V5_FPGA - IO_L20N_T3_38
38 VCCO - VCC1V5_FPGA - IO_L21P_T3_DQS_38
38 VCCO - VCC1V5_FPGA - IO_L21N_T3_DQS_38
38 VCCO - VCC1V5_FPGA - IO_L22P_T3_38
38 VCCO - VCC1V5_FPGA - IO_L22N_T3_38
38 VCCO - VCC1V5_FPGA - IO_L23P_T3_38
38 VCCO - VCC1V5_FPGA - IO_L23N_T3_38
38 VCCO - VCC1V5_FPGA - IO_L24P_T3_38
38 VCCO - VCC1V5_FPGA - IO_L24N_T3_38
38 VCCO - VCC1V5_FPGA - IO_25_VRP_38
39 VCCO - VCC1V5_FPGA - IO_0_VRN_39
39 VCCO - VCC1V5_FPGA - IO_L1P_T0_39
39 VCCO - VCC1V5_FPGA - IO_L1N_T0_39
39 VCCO - VCC1V5_FPGA - IO_L2P_T0_39
39 VCCO - VCC1V5_FPGA - IO_L2N_T0_39
39 VCCO - VCC1V5_FPGA - IO_L3P_T0_DQS_39
39 VCCO - VCC1V5_FPGA - IO_L3N_T0_DQS_39
39 VCCO - VCC1V5_FPGA - IO_L4P_T0_39
39 VCCO - VCC1V5_FPGA - IO_L4N_T0_39
39 VCCO - VCC1V5_FPGA - IO_L5P_T0_39
39 VCCO - VCC1V5_FPGA - IO_L5N_T0_39
39 VCCO - VCC1V5_FPGA - IO_L6P_T0_39
39 VCCO - VCC1V5_FPGA - IO_L6N_T0_VREF_39
39 VCCO - VCC1V5_FPGA - IO_L7P_T1_39
39 VCCO - VCC1V5_FPGA - IO_L7N_T1_39
39 VCCO - VCC1V5_FPGA - IO_L8P_T1_39
39 VCCO - VCC1V5_FPGA - IO_L8N_T1_39
39 VCCO - VCC1V5_FPGA - IO_L9P_T1_DQS_39
39 VCCO - VCC1V5_FPGA - IO_L9N_T1_DQS_39
39 VCCO - VCC1V5_FPGA - IO_L10P_T1_39
39 VCCO - VCC1V5_FPGA - IO_L10N_T1_39
39 VCCO - VCC1V5_FPGA - IO_L11P_T1_SRCC_39
39 VCCO - VCC1V5_FPGA - IO_L11N_T1_SRCC_39
39 VCCO - VCC1V5_FPGA - IO_L12P_T1_MRCC_39
39 VCCO - VCC1V5_FPGA - IO_L12N_T1_MRCC_39
39 VCCO - VCC1V5_FPGA - IO_L13P_T2_MRCC_39
39 VCCO - VCC1V5_FPGA - IO_L13N_T2_MRCC_39
39 VCCO - VCC1V5_FPGA - IO_L14P_T2_SRCC_39
39 VCCO - VCC1V5_FPGA - IO_L14N_T2_SRCC_39
39 VCCO - VCC1V5_FPGA - IO_L15P_T2_DQS_39
39 VCCO - VCC1V5_FPGA - IO_L15N_T2_DQS_39
39 VCCO - VCC1V5_FPGA - IO_L16P_T2_39
89