Revision History - Xilinx VC707 User Manual

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Revision History

The following table shows the revision history for this document.
Date Version
03/05/12 1.0
10/08/12 1.1
02/01/13 1.2
VC707 Evaluation Board
Initial Xilinx release.
Chapter 1, VC707 Evaluation Board
Samtec ASP_134486_01. The board photo in
(U1) Bank 32 was deleted. A note was added about the user clock for
Table 1-15, FPGA pin AN1 changed to AM4 and pin AN2 changed to AM3. In
GTX Transceiver Clock Generation, page
ck. The
LVDS clo Figure 1-10
pin AR42 changed to AT42. In
MGTVCCAUX was updated. In
rail voltage changed to 1.80V. In
Appendix C, Master UCF
Regulatory and Compliance Information
Conformity and markings for waste electrical and electronic equipment (WEEE),
restriction of hazardous substances (RoHS), and CE compliance.
Updated VC707 Board Features,
FPGA Configuration, USB
2
Video Output, I C Bus, Table
57.1 FMC2 HPC Connector (Partially
Figure 1-25. Updated paragraph following
and Table 1-24. Added CPU Reset
Form Factor Board TI Power System
Replaced PTD08D021W with PTD08D210W in
introduction in Appendix C, Master UCF
Semiconductors in References. Added second paragraph to the introduction in
Appendix G, Regulatory and Compliance
www.xilinx.com
Revision
Features: In Table
Figure 1-2
37, 25 MHz LVDS clock changed to 125 MHz
changed fr om 25 MHz to 125 MHz. In
title also
Figure 1-33, switching regulator supply voltage UG63 for
Table 1-29, device type PTD08D021W (V
Table 1-32, values for rail number 3 changed. In
Listing, the entire listing was replaced.
now includes a link to the Declaration of
Table 1-1, Virtex-7 XC7VX485T-2FFG1761C
JTAG, System Clock (SYSCLK_P and
1-15, User I/O, Table 1-26,
Populated). Updated
Table 1-4,
Pushbutton, User Rotary
Cooling. Added
Table
Listing. Added UG483 and removed NXP
Information.
1-1, notes for J37 changed to
was replaced. In Table 1-3, GPGA
Figure 1-10. In
Table
A) power
OUT
Appendix G,
FPGA,
SYSCLK_N), HDMI
Power Management, and
Figure 1-5, Figure 1-16, and
Figure 1-7, Figure 1-19, Figure
Switch, User SMA, and
Table 1-27 and Table 1-28.
1-29. Added third paragraph to the
UG885 (v1.2) February 1, 2013
SGMII
1-23,
VITA
1-20,
PCIe