Vita 57.1 Fmc1 Hpc Connector (Partially Populated); Vita 57.1 Fmc2 Hpc Connector (Partially Populated) - Xilinx VC707 User Manual

Chapter 1: VC707 Evaluation Board Features
Figure 1-32
X-Ref Target - Figure 1-32

VITA 57.1 FMC1 HPC Connector (Partially Populated)

[Figure
The VC707 board implements two instances of the FMC HPC VITA 57.1 specification
connector. This section discusses the FMC1 HPC J35 connector.
Note:
away from the VC707 board.
The VITA 57.1 FMC standard calls for two connector densities: a high pin count (HPC) and
a low pin count (LPC) implementation. A 400 pin 10 x 40 position connector form factor is
used for both versions. The HPC version is fully populated with all 400 pins present. The
LPC version is partially populated with 160 pins.
The 10 x 40 rows of an FMC HPC connector provides pins for up to:
•
•
•
•
•
The VC707 board FMC1 HPC connector J35 implements a subset of the maximum signal
and clock connectivity capabilities:
•
•
•
•
•
•
54
shows the SW11 circuit.
FLASH_A25
FLASH_A24
FPGA_M2
FPGA_M1
FPGA_M0
R341
1.21kΩ
0.1 W
1%
R340
1.21kΩ
0.1 W
1%
GND
Figure 1-32: Configuration Mode and Upper Linear Flash Address Switch
1-2, callout 30]
The FMC1 HPC J35 connector is a keyed connector oriented so that a plug-on card faces
160 single-ended or 80 differential user-defined signals
10 GTX transceivers
2 GTX clocks
4 differential clocks
159 ground and 15 power connections
80 differential user-defined pairs
34 LA pairs (LA00-LA33)
24 HA pairs (HA00-HA23)
22 HB pairs (HB00-HB21)
8 GTX transceivers
2 GTX clocks
www.xilinx.com
VCC1V8
SW11
1
10
9 2
3
8
7 4
5
6
SDA05H1SBD
R339 R337
1.21kΩ 1.21kΩ
0.1 W 0.1 W
1% 1%
R338
1.21kΩ
0.1 W
1%
R226 R227
220Ω 220Ω
0.1 W 0.1 W
1% 1%
UG885_c1_29_030512
VC707 Evaluation Board
UG885 (v1.2) February 1, 2013