Xilinx VC707 User Manual page 32

Evaluation board for the virtex-7 fpga
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Chapter 1: VC707 Evaluation Board Features
Table 1-12:
PCIe Edge Connector Connections (Cont'd)
FPGA (U1)
Net Name
Pin
PCIE_RX3_N
AC5
PCIE_RX4_P
AD4
PCIE_RX4_N
AD3
PCIE_RX5_P
AE6
PCIE_RX5_N
AE5
PCIE_RX6_P
AF4
PCIE_RX6_N
AF3
PCIE_RX7_P
AG6
PCIE_RX7_N
AG5
PCIE_TX0_P
W2
PCIE_TX0_N
W1
PCIE_TX1_P
AA2
PCIE_TX1_N
AA1
PCIE_TX2_P
AC2
PCIE_TX2_N
AC1
PCIE_TX3_P
AE2
PCIE_TX3_N
AE1
PCIE_TX4_P
AG2
PCIE_TX4_N
AG1
PCIE_TX5_P
AH4
PCIE_TX5_N
AH3
PCIE_TX6_P
AJ2
PCIE_TX6_N
AJ1
PCIE_TX7_P
AK4
PCIE_TX7_N
AK3
Si5324_OUT_C_P
AD8
Si5324_OUT_C_N
AD7
PCIE_PRSNT_B
J49 2, 4, 6
PCIE_WAKE_B
AV33
PCIE_PERST_B
AV35
Table 1-13
32
PCIe Edge Connector (P1)
Pin
Name
B28
PETn3
Integrated Endpoint block receive pair
B33
PETp4
Integrated Endpoint block receive pair
B34
PETn4
Integrated Endpoint block receive pair
B37
PETp5
Integrated Endpoint block receive pair
B38
PETn5
Integrated Endpoint block receive pair
B41
PETp6
Integrated Endpoint block receive pair
B42
PETn6
Integrated Endpoint block receive pair
B45
PETp7
Integrated Endpoint block receive pair
B46
PETn7
Integrated Endpoint block receive pair
A16
PERp0
Integrated Endpoint block transmit pair
A17
PERn0
Integrated Endpoint block transmit pair
A21
PERp1
Integrated Endpoint block transmit pair
A22
PERn1
Integrated Endpoint block transmit pair
A25
PERp2
Integrated Endpoint block transmit pair
A26
PERn2
Integrated Endpoint block transmit pair
A29
PERp3
Integrated Endpoint block transmit pair
A30
PERn3
Integrated Endpoint block transmit pair
A35
PERp4
Integrated Endpoint block transmit pair
A36
PERn4
Integrated Endpoint block transmit pair
A39
PERp5
Integrated Endpoint block transmit pair
A40
PERn5
Integrated Endpoint block transmit pair
A43
PERp6
Integrated Endpoint block transmit pair
A44
PERn6
Integrated Endpoint block transmit pair
A47
PERp7
Integrated Endpoint block transmit pair
A48
PERn7
Integrated Endpoint block transmit pair
A13
REFCLK+
Integrated Endpoint block differential clock
pair from PCIe
A14
REFCLK-
Integrated Endpoint block differential clock
pair from PCIe
A1
PRSNT#1
J49 Lane Size Select jumper
B11
WAKE#
Integrated Endpoint block wake signal, not
connected on KC705 Board
A11
PERST
Integrated Endpoint block reset signal
lists the PCIe edge connector connections for Quad 115.
www.xilinx.com
Function
GTXE2_CHANNEL_X0Y16
GTXE2_CHANNEL_X0Y15
GTXE2_CHANNEL_X0Y15
GTXE2_CHANNEL_X0Y14
GTXE2_CHANNEL_X0Y14
GTXE2_CHANNEL_X0Y13
GTXE2_CHANNEL_X0Y13
GTXE2_CHANNEL_X0Y12
GTXE2_CHANNEL_X0Y12
GTXE2_CHANNEL_X0Y19
GTXE2_CHANNEL_X0Y19
GTXE2_CHANNEL_X0Y18
GTXE2_CHANNEL_X0Y18
GTXE2_CHANNEL_X0Y17
GTXE2_CHANNEL_X0Y17
GTXE2_CHANNEL_X0Y16
GTXE2_CHANNEL_X0Y16
GTXE2_CHANNEL_X0Y15
GTXE2_CHANNEL_X0Y15
GTXE2_CHANNEL_X0Y14
GTXE2_CHANNEL_X0Y14
GTXE2_CHANNEL_X0Y13
GTXE2_CHANNEL_X0Y13
GTXE2_CHANNEL_X0Y12
GTXE2_CHANNEL_X0Y12
MGT_BANK_114
MGT_BANK_114
NA
NA
NA
VC707 Evaluation Board
UG885 (v1.2) February 1, 2013
FHG1761
Placement

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