Sgmii Gtx Transceiver Clock Generation - Xilinx VC707 User Manual

Table 1-17: Board Connections for PHY Configuration Pins
Pin Connection on Board
CFG0 V 2.5V
CC
CFG1 Ground
CFG2 V 2.5V
CC
CFG3 V 2.5V
CC
CFG4 V 2.5V
CC
CFG5 PHY_LED_LINK10
CFG6 PHY_LED_RX
The Ethernet connections from FPGA U1 to the 88E1111 PHY device are listed in
Table
Table 1-18: Ethernet Connections, FPGA to PHY Device
FPGA (U1)

SGMII GTX Transceiver Clock Generation

[Figure
An Integrated Circuit Systems ICS844021I chip (U2) generates a high-quality, low-jitter,
125 MHz LVDS clock from a 25 MHz crystal (X3). This clock is sent to FPGA U1, Bank 113
GTX transceiver (clock pins AH8 (P) and AH7 (N)) driving the SGMII interface. Series AC
coupling capacitors are present to allow the clock input of the FPGA to set the common
mode voltage.
VC707 Evaluation Board
UG885 (v1.2) February 1, 2013
Bit[2]
Definition and Value
PHYADR[2] = 1
ENA_PAUSE = 0
ANEG[3] = 1
ANEG[0] = 1
HWCFG_MD[2] = 1
DIS_FC = 1
SEL_BDT = 0
1-18.
Net Name
Pin
AK33 PHY_MDIO
AH31 PHY_MDC
AL31 PHY_INT
AJ33 PHY_RESET
AN2 SGMII_TX_P
AN1 SGMII_TX_N
AM8 SGMII_RX_P
AM7 SGMII_RX_N
1-2, callout 16]
Figure 1-17
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Bit[1]
Definition and Value
PHYADR[1] = 1
PHYADR[4] = 0
ANEG[2] = 1
ENA_XC = 1
HWCFG_MD[1] = 1
DIS_SLEEP = 1
INT_POL = 1
M88E1111 PHY U50
Pin
M1 MDIO
L3 MDC
L1 INT_B
K3 RESET_B
A3 SIN_P
A4 SIN_N
A7 SOUT_P
A8 SOUT_N
shows the Ethernet SGMII clock source.
Feature Descriptions
Bit[0]
Definition and Value
PHYADR[0] = 1
PHYADR[3] = 0
ANEG[1] = 1
DIS_125 = 1
HWCFG_MD[0] = 1
HWCFG_MD[3] = 1
75/50Ω= 0
Name
37