Delta AH500 Programming Manual page 82

SR
Bit 0~bit 15: The conditions of the interrupt
SR626 programs I48~I63 are set by the instruction
IMASK.
Bit 0~bit 15: The conditions of the interrupt
SR627 programs I64~I79 are set by the instruction
IMASK.
Bit 0~bit 15: The conditions of the interrupt
SR628 programs I80~I95 are set by the instruction
IMASK.
Bit 0~bit 15: The conditions of the interrupt
SR629 programs I96~I111 are set by the
instruction IMASK.
Bit 0~bit 15: The conditions of the interrupt
SR630 programs I112~I127 are set by the
instruction IMASK.
Bit 0~bit 15: The conditions of the interrupt
SR631 programs I128~I143 are set by the
instruction IMASK.
Bit 0~bit 15: The conditions of the interrupt
SR632 programs I144~I159 are set by the
instruction IMASK.
Bit 0~bit 15: The conditions of the interrupt
SR633 programs I160~I175 are set by the
instruction IMASK.
Bit 0~bit 15: The conditions of the interrupt
SR634 programs I176~I191 are set by the
instruction IMASK.
Bit 0~bit 15: The conditions of the interrupt
SR635 programs I192~I207 are set by the
instruction IMASK.
Bit 0~bit 15: The conditions of the interrupt
SR636 programs I208~I213 are set by the
instruction IMASK.
Bit 0~bit 15: The conditions of the interrupt
SR637 programs I214~I229 are set by the
instruction IMASK.
Bit 0~bit 15: The conditions of the interrupt
SR638 programs I230~I255 are set by the
instruction IMASK.
Recording the mapping error occurring in
the module table for rack 1 or the error
occurring in the I/○ module of rack 1
*SR655
↓
SR662 Recording the mapping error occurring in
the module table for rack 8 or the error
occurring in the I/○ module of rack 8
Recording the mapping error code
occurring in the module table for rack 1
*SR663 whose slot number is 0
↓
SR674 Recording the mapping error code
occurring in the module table for rack 1
whose slot number is 11
*SR675
Recording the mapping error code
↓
occurring in the module table for rack 2
Function
↓
↓
Ch a pt er 2 De v ic es
OFF STOP

ON
○ ○ ○ ○ ○ FFFF
○ ○ ○ ○ ○ FFFF
○ ○ ○ ○ ○ FFFF
○ ○ ○ ○ ○ FFFF
○ ○ ○ ○ ○ FFFF
○ ○ ○ ○ ○ FFFF
○ ○ ○ ○
× FFFF
○ ○ ○ ○ ○ FFFF
○ ○ ○ ○ ○ FFFF
○ ○ ○ ○ ○ FFFF
○ ○ ○ ○ ○ FFFF
○ ○ ○ ○ ○ FFFF
○ ○ ○ ○ ○ FFFF
○ ○ ○ ○ ○
0
○ ○ ○ ○ ○
0
○ ○ ○ ○ ○
0
RUN
 
RUN STOP
FFF
– – R
F
FFF
– – R
F
FFF
– – R
F
FFF
– – R
F
FFF
– – R
F
FFF
– – R
F
FFF
– – R
F
FFF
– – R
F
FFF
– – R
F
FFF
– – R
F
FFF
– – R
F
FFF
– – R
F
FFF
– – R
F
– – R 0
– – R 0
– – R 0
2 - 6 3