Delta AH500 Programming Manual page 363

Before the instruction
is executed
After the instruction
is executed
Additional remark:
1. If S +n-1, S +n-1, or D+n-1 exceeds the device range, the instruction is not executed, SM0 is
1 2
ON, and the error code in SR0 is 16#2003.
2. If n is less than 1, or if n is larger than 256, the instruction is not executed, SM0 is ON, and the
error code in SR0 is 16#200B.
3. Explanation of matrix instructions:

A matrix is composed of more than one 16-bit register. The number of registers in a
matrix is the length of the array n. There are 16×n bits in a matrix, and the matrix
operation is performed on one bit at a time.

The matrix instruction takes the 16×n bits in a matrix as a string of bits, rather than takes
them as values. The matrix operation is performed on one specified bit.

The matrix instruction mainly processes the one-to-many status or the many-to-many
status, such as the moving, the copying, the comparing, and the searching. It is a handy
and important applied instruction.

When the matrix instruction is executed, users need a 16-bit register to specify a certain
bit among the 16n bits in the matrix for the operation. The 16-bit register is called the
pointer, and is specified by users. The value in the register is within the range between 0
and 16n-1, and corresponds to the bit within the range between b0 and b16n-1.

The shift of the specified data, or the rotation of the specified data can be involved in the
matrix operation. Besides, the bit number decreases from the left to the right, as
illustrated below.
Y0
Y1
Y2
Mn-1 b16n- 1

The width of the matrix (C) is 16 bits.

Pr represents the pointer. When the value in Pr is 15, b15 is specified.
Example: The following matrix is composed of the three 16-bit devices Y0, Y1, and Y2.
The data in Y0 is 16#AAAA, the data in Y1 is 16#5555, and the data in Y2 is
16#AAFF.
S1
b15
Y0
1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1
Y1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1
1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1
Y2
S2 b15
Y10
0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0
Y11 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0
0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0
Y12
b15
D
Y20
0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0
Y21 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0
Y22
Left
Width: 16 bits
b15
1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1
b31
1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1
b47 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1
0 0 0 1 0 0 1 0 0 0
1 1
0 0 0 0 0 0 0 0
C ha pt er 6 A p pl i e d In s tr uc t io ns
b0
b0
b0
Right
b0
b16
b32
1 1 0 1 0 0
1 1 0 1
0 0
6 - 1 9 5