Write Enable And Output Enable Control Signals; Sram Data Signals, Chip Enables, And Byte Enables - Xilinx Spartan-3 User Manual

Write Enable and Output Enable Control Signals

Write Enable and Output Enable Control Signals
Both 256Kx16 SRAMs share common output enable (OE#) and write enable (WE#) control
lines, as shown in
Connector (refer to
Table 2-2: External SRAM Control Signal Connections to Spartan-3 FPGA

SRAM Data Signals, Chip Enables, and Byte Enables

The data signals, chip enables, and byte enables are dedicated connections between the
FPGA and SRAM.
IC10 in
SRAM, drive the associated chip enable pin High.
Table 2-3: SRAM IC10 Connections
Spartan-3 Starter Kit Board User Guide
UG130 (v1.1) May 13, 2005
Table 2-2. These control signals also connect to the A1 Expansion
"Expansion Connectors," page
Signal
OE#
WE#
Table 2-3
Figure A-8. Table 2-4
Signal
IO15
IO14
IO13
IO12
IO11
IO10
IO9
IO8
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
CE1 (chip enable IC10)
UB1 (upper byte enable IC10)
LB1 (lower byte enable IC10)
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47).
FPGA Pin A1 Expansion Connector Pin
K4
G3
shows the FPGA pin connections to the SRAM designated
shows the FPGA pin connections to SRAM IC11. To disable an
FPGA Pin A1 Expansion Connector Pin
R1
P1
L2
J2
H1
F2
P8
D3
B1
C1
C2
R5
T5
R6
T8
N7
P7
T4
P6
16
18
19
17
15
13
11
9
7
5
13
R