Device Control Register (Dcr); Interrupts - Xilinx ML40 Series User Manual

Chapter 2: ML40x Embedded Processor Reference System

Device Control Register (DCR)

The DCR bus offers a very simple interface protocol and is used for accessing control and
status registers in various devices. It allows for register access to various devices without
overloading the OPB and PLB interfaces. Because DCR devices are generally accessed
infrequently and do not have high-performance requirements, they are used throughout
the reference design for functions, such as error status registers, interrupt controllers, and
device initialization logic.
An OPB-to-DCR Bridge is instantiated to locate the 4-KB DCR space within the general
system memory space. The DCR slave devices connected to the OPB-to-DCR Bridge
include:
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The DCR specification requires that the DCR master and slave clocks be synchronous to
each other and related in frequency by an integer multiple. It is important to be aware of
the clock domains of each of the DCR devices to ensure proper functionality.

Interrupts

An interrupt controller for interrupts is controlled through the OPB. It allows multiple
edge or level sensitive interrupts from peripherals to be OR'ed together back to the CPU.
The ability for bitwise masking of individual interrupts is also provided. The connections
from the IP to the interrupt controller are:
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PLB Arbiter (if enabled)
VGA TFT LCD Controller
UART
Microprocessor debug module (MicroBlaze system)
Ethernet controller
PS/2 Port #1
PS/2 Port #2
External USB chip
System ACE MPU
AC97 sound controller (play buffer)
AC97 sound controller (record buffer)
Ethernet PHY
IIC controller (PPC405 system)
www.xilinx.com ML40x EDK Processor Reference Design
UG082 (v5.0) June 30, 2006
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