Pci Express Clock; Pci Express Lane Size Select Jumper J32; Pcie Edge Connector Connections - Xilinx KC705 User Manual

The PCIe clock is input from the edge connector. It is AC coupled to the FPGA through the
MGTREFCLK1 pins of Quad 115. PCIE_CLK_Q0_P is connected to FPGA U1 pin U8, and the _N
net is connected to pin U7. The PCI Express clock circuit is shown in
X-Ref Target - Figure 1-15
PCIe lane width/size is selected via jumper J32
is 8-lane (J32 pins 5 and 6 jumpered).
X-Ref Target - Figure 1-16
Table 1-11 lists the PCIe edge connector connections.
Table 1-11: PCIe Edge Connector Connections
Schematic Net FPGA Pin
Name (U1)
PCIE_RX0_P M6
PCIE_RX0_N M5
PCIE_RX1_P P6
PCIE_RX1_N P5
PCIE_RX2_P R4
PCIE_RX2_N R3
PCIE_RX3_P T6
KC705 Evaluation Board
UG810 (v1.8) March 20, 2018
P1
PCI Express
Eight-Lane
Edge connector
OE
A12
GND
A13
PCIE_CLK_Q0_C_P
REFCLK+
A14
PCIE_CLK_Q0_C_N
REFCLK-
A15
GND
GND
Figure 1-15: PCI Express Clock
PCIE_PRSNT_X1
1
PCIE_PRSNT_X4
3
PCIE_PRSNT_X8 5
Figure 1-16: PCI Express Lane Size Select Jumper J32
PCIe Edge
PCIe Edge
Connector
Pin Name
Pin
B14 PETp0
B15 PETn0
B19 PETp1
B20 PETn1
B23 PETp2
B24 PETn2
B27 PETp3
www.xilinx.com
Chapter 1: KC705 Evaluation Board Features
C544
0.01μF 25V
X7R
PCIE_CLK_Q0_P
PCIE_CLK_Q0_N
C545
0.01μF 25V
X7R
UG810_c1_15_031214
(Figure 1-16). The default lane size selection
J32
PCIE_PRSNT_B
2
4
6
UG810_c1_16_031214
Function
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Figure 1-15.
FFG900 Placement
GTXE2_CHANNEL_X0Y7
GTXE2_CHANNEL_X0Y7
GTXE2_CHANNEL_X0Y6
GTXE2_CHANNEL_X0Y6
GTXE2_CHANNEL_X0Y5
GTXE2_CHANNEL_X0Y5
GTXE2_CHANNEL_X0Y4
36
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