Xilinx KC705 User Manual page 40

Table 1-13: GTX Quad 116 to PCIe Edge Connector Connections (Cont'd)
Quad 116 Pin Name
Pin (U1)
MGTXRXP2_116_P6
MGTXRXN2_116_P5
MGTXTXP3_116_L4
MGTXTXN3_116_L3
MGTXRXP3_116_M6
MGTXRXN3_116_M5
MGTREFCLK0P_116_L8
MGTREFCLK0N_116_L7
MGTREFCLK1P_116_N8
MGTREFCLK1N_116_N7
For more information refer to 7 Series FPGAs GTX Transceivers User Guide (UG476)
and 7 Series FPGAs Integrated Block for PCI Express User Guide (AXI) (PG054)
KC705 Evaluation Board
UG810 (v1.8) March 20, 2018
FPGA
Schematic Net Name
P6 PCIE_RX1_P
P5 PCIE_RX1_N
L4 PCIE_TX0_P
L3 PCIE_TX0_N
M6 PCIE_RX0_P
M5 PCIE_RX0_N
L8 SI5326_OUT_C_P
L7 SI5326_OUT_C_N
N8 FMC_LPC_GBTCLK0_M2C_C_P
N7 FMC_LPC_GBTCLK0_M2C_C_N
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Chapter 1: KC705 Evaluation Board Features
PCIe Edge PCIe
Connector Edge in
Pin Name
B19 PETp1
B20 PETn1
A16 PERp0
A17 PERn0
B14 PETp0
B15 PETn0
Send Feedback
FFG900 Placement
GTXE2_CHANNEL_X0Y6
GTXE2_CHANNEL_X0Y6
GTXE2_CHANNEL_X0Y7
GTXE2_CHANNEL_X0Y7
GTXE2_CHANNEL_X0Y7
GTXE2_CHANNEL_X0Y7
MGT_BANK_116
MGT_BANK_116
MGT_BANK_116
MGT_BANK_116
[Ref 12]
[Ref 13].
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