10/100/1000 Tri-Speed Ethernet Phy; Phy Default Interface Mode; Board Connections For Phy Configuration Pins - Xilinx KC705 User Manual

Table 1-15: SFP+ Module Control and Status (Cont'd)
SFP Control/Status Signal
SFP_LOS
Notes:
1. Default jumper shunt positions are shown in bold text.

10/100/1000 Tri-Speed Ethernet PHY

[Figure 1-2, callout 15]
The KC705 board utilizes the Marvell Alaska PHY device (88E1111) U37 for Ethernet
communications at 10, 100, or 1000 Mb/s. The board supports MII, GMII, RGMII, and SGMII
interfaces from the FPGA to the PHY
Ethernet cable is through a Halo HFJ11-1G01E RJ-45 connector (P3) with built-in magnetics.
Table 1-16: PHY Default Interface Mode
Mode
GMII/MII to copper (default)
SGMII to copper, no clock
RGMII
On power-up, or on reset, the PHY is configured to operate in GMII mode with PHY address
0b00111 using the settings shown in
software commands passed over the MDIO interface.
Table 1-17: Board Connections for PHY Configuration Pins
Connection on
Pin
Board
CFG0 V
CC
CFG1 Ground
CFG2 V
CC
CFG3 V
CC
CFG4 V
CC
CFG5 V
CC
CFG6 PHY_LED_RX
KC705 Evaluation Board
UG810 (v1.8) March 20, 2018
Test Point J8
High = Loss of Receiver Signal
Low = Normal Operation
(Table
J29
Jumper over pins 1-2
Jumper over pins 2-3
Jumper over pins 1-2
Table
Bit[2] Definition and
Value
2.5V PHYADR[2] = 1
ENA_PAUSE = 0
2.5V ANEG[3] = 1
2.5V ANEG[0] = 1
2.5V HWCFG_MD[2] = 1
2.5V DIS_FC = 1
SEL_BDT = 0
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Chapter 1: KC705 Evaluation Board Features
Board Connection
1-16). The PHY connection to a user-provided
Jumper Settings
J30
Jumper over pins 1-2
Jumper over pins 2-3
No jumper
1-17. These settings can be overwritten via
Bit[1] Definition and
Value
PHYADR[1] = 1
PHYADR[4] = 0
ANEG[2] = 1
ENA_XC = 1
HWCFG_MD[1] = 1
DIS_SLEEP = 1
INT_POL = 1
J64
No jumper
No jumper
Jumper on
Bit[0] Definition and
Value
PHYADR[0] = 1
PHYADR[3] = 0
ANEG[1] = 1
DIS_125 = 1
HWCFG_MD[0] = 1
HWCFG_MD[3] = 1
75/50Ω= 0
43
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