Xilinx KC705 User Manual page 89

set_property PACKAGE_PIN W28 [get_ports REC_CLOCK_C_N]
set_property IOSTANDARD LVDS_25 [get_ports REC_CLOCK_C_N]
set_property PACKAGE_PIN W27 [get_ports REC_CLOCK_C_P]
set_property IOSTANDARD LVDS_25 [get_ports REC_CLOCK_C_P]
set_property PACKAGE_PIN AG24 [get_ports SI5326_INT_ALM_LS]
set_property IOSTANDARD LVCMOS25 [get_ports SI5326_INT_ALM_LS]
set_property PACKAGE_PIN AE20 [get_ports SI5326_RST_LS]
set_property IOSTANDARD LVCMOS25 [get_ports SI5326_RST_LS]
#SMA MGT REFCLK
set_property PACKAGE_PIN J7 [get_ports SMA_MGT_REFCLK_N]
set_property PACKAGE_PIN J8 [get_ports SMA_MGT_REFCLK_P]
#EMCCLK
set_property PACKAGE_PIN R24 [get_ports FPGA_EMCCLK]
set_property IOSTANDARD LVCMOS25 [get_ports FPGA_EMCCLK]
#DDR3
#DATA
set_property PACKAGE_PIN AA15 [get_ports DDR3_D0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D0]
set_property PACKAGE_PIN AA16 [get_ports DDR3_D1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D1]
set_property PACKAGE_PIN AC14 [get_ports DDR3_D2]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D2]
set_property PACKAGE_PIN AD14 [get_ports DDR3_D3]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D3]
set_property PACKAGE_PIN AA17 [get_ports DDR3_D4]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D4]
set_property PACKAGE_PIN AB15 [get_ports DDR3_D5]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D5]
set_property PACKAGE_PIN AE15 [get_ports DDR3_D6]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D6]
set_property PACKAGE_PIN Y15 [get_ports DDR3_D7]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D7]
set_property PACKAGE_PIN AB19 [get_ports DDR3_D8]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D8]
set_property PACKAGE_PIN AD16 [get_ports DDR3_D9]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D9]
set_property PACKAGE_PIN AC19 [get_ports DDR3_D10]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D10]
set_property PACKAGE_PIN AD17 [get_ports DDR3_D11]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D11]
set_property PACKAGE_PIN AA18 [get_ports DDR3_D12]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D12]
set_property PACKAGE_PIN AB18 [get_ports DDR3_D13]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D13]
set_property PACKAGE_PIN AE18 [get_ports DDR3_D14]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D14]
set_property PACKAGE_PIN AD18 [get_ports DDR3_D15]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D15]
set_property PACKAGE_PIN AG19 [get_ports DDR3_D16]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D16]
set_property PACKAGE_PIN AK19 [get_ports DDR3_D17]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D17]
set_property PACKAGE_PIN AG18 [get_ports DDR3_D18]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D18]
set_property PACKAGE_PIN AF18 [get_ports DDR3_D19]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D19]
KC705 Evaluation Board
UG810 (v1.8) March 20, 2018
Appendix C: Master Constraints File Listing
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