Ddr3 Memory Module - Xilinx KC705 User Manual

Table 1-3: I/O Voltage Rails
U1 FPGA Bank
Bank 0
Bank 12
Bank 13
Bank 14
Bank 15
Bank 16
Bank 17
Bank 18
Bank 32
Bank 33
Bank 34
Notes:
1. The VADJ_FPGA rail can support 1.8V, 2.5V, or 3.3V. For more information on VADJ_FPGA see
page 71.

DDR3 Memory Module

[Figure 1-2, callout 2]
The memory module at J1 is a 1 GB DDR3 small outline dual-inline memory module
(SODIMM). It provides volatile synchronous dynamic random access memory (SDRAM) for
storing user code and data.
• Part number: MT8JTF12864HZ-1G6G1 (Micron Technology)
• Supply voltage: 1.5V
• Datapath width: 64 bits
• Data rate: Up to 1,600 MT/s
The DDR3 interface is implemented across I/O banks 32, 33, and 34. Each bank is a 1.5V
high-performance (HP) bank. The VRP/VRN DCI resistor connection to bank 33 is cascaded
to the data interface banks 32 and 34 by adding the DCI cascade constraint to the XDC:
# Set DCI_CASCADE
set_property slave_banks {32 34} [get_iobanks 33]
An external 0.75V reference VTTREF is provided for data interface banks 32 and 34. Any
interface connected to these banks that requires a reference voltage must use this FPGA
voltage reference. The connections between the DDR 3 memory and the FPGA are listed in
Table 1-4.
KC705 Evaluation Board
UG810 (v1.8) March 20, 2018
Power Supply Rail Net Name
(1)
(1)
(1)
(1)
(1)
www.xilinx.com
Chapter 1: KC705 Evaluation Board Features
VCC2V5_FPGA
VADJ_FPGA
VADJ_FPGA
VCC2V5_FPGA
VCC2V5_FPGA
VADJ_FPGA
VADJ_FPGA
VADJ_FPGA
VCC1V5_FPGA
VCC1V5_FPGA
VCC1V5_FPGA
Voltage
2.5V
2.5V (default)
2.5V (default)
2.5V
2.5V
2.5V (default)
2.5V (default)
2.5V (default)
1.5V
1.5V
1.5V
Power Management,
14
Send Feedback