Fpga U1 To Sfp+ Module Connections; Sfp+ Module Control And Status - Xilinx KC705 User Manual

Table 1-14 lists the SFP+ module RX and TX connections to the FPGA.
Table 1-14: FPGA U1 to SFP+ Module Connections
FPGA Pin (U1)
G3
G4
H1
H2
Y20
Notes:
1. On KC705 boards prior to Rev 1.1, SFP+ connector P5 pin 18 RD_P is connected to net SFP_RX_N, and pin 19 RD_N
is connected to net SFP_RX_P.
2. On KC705 boards prior to Rev 1.1, SFP+ connector P5 pin 18 TD_P is connected to net SFP_TX_N, and pin 19 TD_N
is connected to net SFP_TX_P.
3. SFP_TX_DISABLE_TRANS I/O standard = LVCMOS25.
Table 1-15 lists the SFP+ module control and status connections to the FPGA.
Table 1-15: SFP+ Module Control and Status
SFP Control/Status Signal
SFP_TX_FAULT
SFP_TX_DISABLE
SFP_MOD_DETECT
SFP_RS0
SFP_RS1
KC705 Evaluation Board
UG810 (v1.8) March 20, 2018
Schematic Net Name
SFP_RX_N
SFP_RX_P
SFP_TX_N
SFP_TX_P
(3)
SFP_TX_DISABLE_TRANS
Test Point J10
High = Fault
Low = Normal Operation
Jumper J4
Off = FP Disabled
On = SFP Enabled
Test Point J9
High = Module Not Present
Low = Module Present
Jumper J27
Jumper Pins 1-2 = Full RX Bandwidth
Jumper Pins 2-3 = Reduced RX Bandwidth
Jumper J28
Jumper Pins 1-2 = Full TX Bandwidth
Jumper Pins 2-3 = Reduced TX Bandwidth
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Chapter 1: KC705 Evaluation Board Features
SFP+ Pin (P5) SFP+ Pin Name (P5)
12
13
19
18
3
Board Connection
Send Feedback
(1)
RD_N
(1)
RD_P
(2)
TX_N
(2)
TX_P
TX_DISABLE
42