Configuration Mode And Upper Linear Flash Address Switch (Sw13); Fpga_Prog_B Pushbutton Sw14; Configuration Mode And Upper Linear Flash Address Switch - Xilinx KC705 User Manual

Figure 1-33 shows SW14.
X-Ref Target - Figure 1-33

Configuration Mode and Upper Linear Flash Address Switch (SW13)

[Figure 1-2, callout 29]
FPGA Configuration Mode: DIP switch SW13 positions 3, 4, and 5 control which
configuration mode is used at power-up or when the PROG pushbutton is pressed.
Linear BPI Flash Memory Upper Addresses: DIP switch SW13 positions 1 and 2 control the
setting of address bits FLASH_A25 and FLASH_A24. The mode signals FPGA_M2, _M1 and
_M0 are connected to FPGA U1 pins AB1, AB2 and AB5 respectively. The BPI flash memory
U58 address signals FLASH_A24 AND FLASH_A25 are connected to FPGA U1 pins M23 and
M22 respectively. Configuration mode is used at power-up or when the PROG pushbutton
is pressed.
Figure 1-34 shows the SW13 circuit.
X-Ref Target - Figure 1-34
FLASH_A25
FLASH_A24
FPGA_M2
FPGA_M1
FPGA_M0
KC705 Evaluation Board
UG810 (v1.8) March 20, 2018
FPGA_PROG_B
Figure 1-33: FPGA_PROG_B Pushbutton SW14
R396 R398
1.21kΩ 1.21kΩ
0.1 W 0.1 W
1% 1%
R397
1.21kΩ
0.1 W
1%
GND
Figure 1-34: Configuration Mode and Upper Linear Flash Address Switch
www.xilinx.com
Chapter 1: KC705 Evaluation Board Features
VCC2V5
R295
4.7kΩ
0.1 W
SW14
5%
1 4
2 3
GND
UG810_c1_33_031214
VCC2V5
SW13
1
10
2
9
8 3
7 4
6 5
SDA05H1SBD
R400
1.21kΩ
0.1 W
1%
R399
1.21kΩ
0.1 W
1%
R401 R402
220Ω 220Ω
0.1 W 0.1 W
1% 1%
UG810_c1_34_031214
62
Send Feedback