Xilinx KC705 User Manual page 18

Table 1-4: DDR3 Memory Connections to the FPGA (Cont'd)
U1 FPGA
Pin
Y18
Y19
AK18
AJ18
AJ16
AH16
AJ7
AH7
AH1
AG2
AG3
AG4
AD1
AD2
AD8
AC10
AK3
AC12
AE8
AJ9
AE9
AC11
AD9
AF10
AE10
AH10
AG10
AF11
AE11
The KC705 DDR3 SODIMM interface adheres to the constraints guidelines documented in
the DDR3 Design Guidelines section of 7 Series FPGAs Memory Interface Solutions
KC705 Evaluation Board
UG810 (v1.8) March 20, 2018
Net Name
DDR3_DQS1_N
DDR3_DQS1_P
DDR3_DQS2_N
DDR3_DQS2_P
DDR3_DQS3_N
DDR3_DQS3_P
DDR3_DQS4_N
DDR3_DQS4_P
DDR3_DQS5_N
DDR3_DQS5_P
DDR3_DQS6_N
DDR3_DQS6_P
DDR3_DQS7_N
DDR3_DQS7_P
DDR3_ODT0
DDR3_ODT1
DDR3_RESET_B
DDR3_S0_B
DDR3_S1_B
DDR3_TEMP_EVENT
DDR3_WE_B
DDR3_CAS_B
DDR3_RAS_B
DDR3_CKE0
DDR3_CKE1
DDR3_CLK0_N
DDR3_CLK0_P
DDR3_CLK1_N
DDR3_CLK1_P
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Chapter 1: KC705 Evaluation Board Features
J1 DDR3 Memory
I/O Standard
Pin
Number
DIFF_SSTL15 27
DIFF_SSTL15 29
DIFF_SSTL15 45
DIFF_SSTL15 47
DIFF_SSTL15 62
DIFF_SSTL15 64
DIFF_SSTL15 135
DIFF_SSTL15 137
DIFF_SSTL15 152
DIFF_SSTL15 154
DIFF_SSTL15 169
DIFF_SSTL15 171
DIFF_SSTL15 186
DIFF_SSTL15 188
SSTL15 116
SSTL15 120
LVCMOS15 30
SSTL15 114
SSTL15 121
SSTL15 198
SSTL15 113
SSTL15 115
SSTL15 110
SSTL15 73
SSTL15 74
DIFF_SSTL15 103
DIFF_SSTL15 101
DIFF_SSTL15 104
DIFF_SSTL15 102
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Pin Name
DQS1_N
DQS1_P
DQS2_N
DQS2_P
DQS3_N
DQS3_P
DQS4_N
DQS4_P
DQS5_N
DQS5_P
DQS6_N
DQS6_P
DQS7_N
DQS7_P
ODT0
ODT1
RESET_B
S0_B
S1_B
EVENT_B
WE_B
CAS_B
RAS_B
CKE0
CKE1
CK0_N
CK0_P
CK1_N
CK1_P
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