A-3: Kc705 Jumper Locations - Xilinx KC705 User Manual

Table A-3: KC705 Default Jumper Settings (Cont'd)
Header
Callout Reference
Designator
5 J56
6 J65
7 J68
3-pin
8 J27
9 J28
10 J29
11 J30
12 J47
13 J48
14 J69
2x3
15 J32
X-Ref Target - Figure A-3
9 8
10
KC705 Evaluation Board
UG810 (v1.8) March 20, 2018
Jumper
Position
None U56 UCD9248 RESET_B = LOGIC 1 (NOT RESET)
1-2 FMC VADJ = ON
1-2 XADC_VCC5V0 =VCC5V0 (5V)
2-3 SFP RX BW = FULL
2-3 SFP TX BW = FULL
1-2 U32 EPHY CONFIG5 = LOGIC 1
1-2 U32 EPHY CONFIG4 = LOGIC 1
1-2 XADC_VREFP = REF3012 XADC_VREF
2-3 XADC_VCC = ADP123 1.85V
1-2 REF3012 VIN = XADC_VCC5V0
5-6 PCIe lane width = 8
1
7
13
14
11
15
12
3 2
Figure A-3: KC705 Jumper Locations
www.xilinx.com
Appendix A: Default Switch and Jumper Settings
Description
6
4
5
Schematic
0381502 Page
40
36
31
22
22
25
25
31
31
31
21
UG810_aA_03_111414
85
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