Xilinx KC705 User Manual page 17

Table 1-4: DDR3 Memory Connections to the FPGA (Cont'd)
U1 FPGA
Pin
AH2
AH4
AJ4
AK1
AJ1
AF1
AF2
AE4
AE3
AF3
AF5
AE1
AE5
AC1
AD3
AC4
AC5
AE6
AD6
AC2
AD4
Y16
AB17
AF17
AE16
AK5
AJ3
AF6
AC7
AC15
AC16
KC705 Evaluation Board
UG810 (v1.8) March 20, 2018
Net Name
DDR3_D43
DDR3_D44
DDR3_D45
DDR3_D46
DDR3_D47
DDR3_D48
DDR3_D49
DDR3_D50
DDR3_D51
DDR3_D52
DDR3_D53
DDR3_D54
DDR3_D55
DDR3_D56
DDR3_D57
DDR3_D58
DDR3_D59
DDR3_D60
DDR3_D61
DDR3_D62
DDR3_D63
DDR3_DM0
DDR3_DM1
DDR3_DM2
DDR3_DM3
DDR3_DM4
DDR3_DM5
DDR3_DM6
DDR3_DM7
DDR3_DQS0_N
DDR3_DQS0_P
www.xilinx.com
Chapter 1: KC705 Evaluation Board Features
J1 DDR3 Memory
I/O Standard
Pin
Number
SSTL15 159
SSTL15 146
SSTL15 148
SSTL15 158
SSTL15 160
SSTL15 163
SSTL15 165
SSTL15 175
SSTL15 177
SSTL15 164
SSTL15 166
SSTL15 174
SSTL15 176
SSTL15 181
SSTL15 183
SSTL15 191
SSTL15 193
SSTL15 180
SSTL15 182
SSTL15 192
SSTL15 194
SSTL15 11
SSTL15 28
SSTL15 46
SSTL15 63
SSTL15 136
SSTL15 153
SSTL15 170
SSTL15 187
DIFF_SSTL15 10
DIFF_SSTL15 12
Send Feedback
Pin Name
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DQS0_N
DQS0_P
17