Configuration Options; Mode Switch Sw13 Settings - Xilinx KC705 User Manual

Table 1-34: XADC Header J46 Pinout (Cont'd)
Net Name
GND
XADC_GPIO_3, 2, 1, 0

Configuration Options

The FPGA on the KC705 board can be configured by the following methods:
• Master BPI (uses the Linear BPI flash memory)
• Master SPI (uses the Quad SPI flash memory)
• JTAG (uses the USB-to-JTAG Bridge or Download cable). See
for more information
See 7 Series FPGAs Configuration User Guide (UG470)
modes.
The method used to configure the FPGA is controlled by the mode pin (M2, M1, M0)
settings selected through DIP switch SW13.
settings.
Table 1-35: Mode Switch SW13 Settings
Configuration Mode
Master SPI
Master BPI
JTAG
KC705 Evaluation Board
UG810 (v1.8) March 20, 2018
J46 Pin
Number
16 Digital Ground (board) Reference
19, 20, 17, 18 Digital I/O. These pins should come from the same bank. These I/Os
should not be shared with other functions because they are required to
support 3-state operation.
Mode Pins (M[2:0])
001
010
101
www.xilinx.com
Chapter 1: KC705 Evaluation Board Features
Description
USB JTAG Module, page 26
[Ref 2] for details on configuration
Table 1-35 lists the supported mode switch
Bus Width CCLK Direction
x1, x2, x4 Output
x8, x16 Output
x1 Not Applicable
80
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