Usb-To-Uart Bridge - Xilinx KC705 User Manual

Evaluation board for the kintex-7 fpga
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Table 1-18: Ethernet PHY Connections (Cont'd)
U1 FPGA Pin
U28
R19
T27
T26
T28
K30
M28
N29
M27
N27
N25
M29
L28
J26
K26
L30
J28
J4
J3
H6
H5
Details about the tri-mode Ethernet MAC core are provided in LogiCORE IP Tri-Mode
Ethernet MAC User Guide (PG051)
For more information about the Marvell 88E1111, see
For more information about the ICS 844021-01, see

USB-to-UART Bridge

[Figure
1-2, callout 17]
The KC705 board contains a Silicon Labs CP2103GM USB-to-UART bridge device (U12)
which allows a connection to a host computer with a USB port. The USB cable is supplied in
the Evaluation Kit (standard-A plug to host computer, mini-B plug to KC705 board
KC705 Evaluation Board
UG810 (v1.8) March 20, 2018
Schematic Net Name
PHY_RXD3
PHY_RXD4
PHY_RXD5
PHY_RXD6
PHY_RXD7
PHY_TXC_GTXCLK
PHY_TXCLK
PHY_TXER
PHY_TXCTL_TXEN
PHY_TXD0
PHY_TXD1
PHY_TXD2
PHY_TXD3
PHY_TXD4
PHY_TXD5
PHY_TXD6
PHY_TXD7
SGMII_TX_P
SGMII_TX_N
SGMII_RX_P
SGMII_RX_N
[Ref
14].
www.xilinx.com
Chapter 1: KC705 Evaluation Board Features
M88E1111 (U37)
I/O Standard
Pin Number
LVCMOS25
B3
LVCMOS25
C4
LVCMOS25
A1
LVCMOS25
A2
LVCMOS25
C5
LVCMOS25
E2
LVCMOS25
D1
LVCMOS25
F2
LVCMOS25
E1
LVCMOS25
F1
LVCMOS25
G2
LVCMOS25
G3
LVCMOS25
H2
LVCMOS25
H1
LVCMOS25
H3
LVCMOS25
J1
LVCMOS25
J2
LVCMOS25
A3
LVCMOS25
A4
LVCMOS25
A7
LVCMOS25
A8
[Ref
15].
[Ref
16].
Pin Name
RXD3
RXD4
RXD5
RXD6
RXD7
GTXCLK
TXCLK
TXER
TXEN
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
SIN_P
SIN_N
SOUT_P
SOUT_N
45
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