Fmc_Vadj Voltage Control; Cooling Fan Control - Xilinx KC705 User Manual

Table 1-30: Onboard Power System Devices (Cont'd)
Reference
Device Type
Designator
TPS51200DR U33
Notes:
1. See Table 1-31.
2. See Table 1-32.
3. See Table 1-33.

FMC_VADJ Voltage Control

The FMC_VADJ rail is set to 2.5V. When the KC705 board is powered on, the state of the
FMC_VADJ_ON_B signal wired to header J65 is sampled by the Texas Instruments UCD9248
controller U55. If a jumper is installed on J65, signal FMC_VADJ_ON_B is held low, and the TI
controller U55 energizes the FMC_VADJ rail at power on.
Because the rail turn on decision is made at power on time based on the presence of the J65
jumper, removing the jumper at J65 after the board is powered up does not affect the 2.5V
power delivered to the FMC_VADJ rail and it remains on.
A jumper installed at J65 is the default setting.
If a jumper is not installed on J65, signal FMC_VADJ_ON_B is High, and the KC705 board
does not energize the FMC_VADJ 2.5V at power on. In this mode you can control when to
turn on FMC_VADJ and to what voltage level (1.8V - 3.3V). With FMC_VADJ off, the FPGA still
configures and has access to the TI controller PMBUS (on bank 32) along with the
FMC_VADJ_ON_B signal (on bank 15 pin J27). The combination of these allows you to
develop code to command the FMC_VADJ rail to be set to something other than the default
setting of 2.5V. After the new FMC_VADJ voltage level has been programmed into TI
controller U55, the FMC_VADJ_ON_B signal can be driven Low by the user logic and the
FMC_VADJ rail comes up at the new FMC_VADJ voltage level. Installing a jumper at J65 after
a KC705 board powers up in this mode turns on the FMC_VADJ rail.
For access to Texas Instruments fusion tools documentation describing PMBUS
programming for the UCD9248 digital power controller, see

Cooling Fan Control

Cooling fan RPM is controlled and monitored by user-created IP in the FPGA using the fan
control circuit is shown in
FPGA U1 is cooled by a 12V DC fan connected to J61. 12V
J61 pin 2. The fan GND return is provided through J61 pin 1 and transistor Q17. Fan speed
is controlled by a pulse-width-modulated signal from FPGA U1 pin L26 (on bank 15) driving
the gate of Q17. The default unprogrammed FPGA fan operation mode is ON. The fan speed
tachometer signal on J61 pin 3 can be monitored on FPGA U1 pin U22 (on bank 14).
KC705 Evaluation Board
UG810 (v1.8) March 20, 2018
Description
Tracking Regulator, 3A
Figure 1-36.
www.xilinx.com
Chapter 1: KC705 Evaluation Board Features
Power Rail Net Power Rail
Name Voltage
VTTDDR
[Ref 19].
is provided to the fan through
DC
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Schematic
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