Lpc Connections, J2 To Fpga U1 - Xilinx KC705 User Manual

• 2 differential clocks
• 61 ground and 9 power connections
Table 1-29: LPC Connections, J2 to FPGA U1
J2 Pin Schematic Net Name
C2 FMC_LPC_DP0_C2M_P
C3 FMC_LPC_DP0_C2M_N
C6 FMC_LPC_DP0_M2C_P
C7 FMC_LPC_DP0_M2C_N
C10 FMC_LPC_LA06_P
C11 FMC_LPC_LA06_N
C14 FMC_LPC_LA10_P
C15 FMC_LPC_LA10_N
C18 FMC_LPC_LA14_P
C19 FMC_LPC_LA14_N
C22 FMC_LPC_LA18_CC_P
C23 FMC_LPC_LA18_CC_N
C26 FMC_LPC_LA27_P
C27 FMC_LPC_LA27_N
C30 FMC_LPC_IIC_SCL
C31 FMC_LPC_IIC_SDA
C34 GA0=0=GND
C35 VCC12_P
C37 VCC12_P
C39 VCC3V3
G2 FMC_LPC_CLK1_M2C_P
KC705 Evaluation Board
UG810 (v1.8) March 20, 2018
U1
I/O J2
FPGA
Standard Pin
Pin
F2 D1
F1 D4
F6 D5
F5 D8
LVDS AK20 D9
LVDS AK21 D11
LVDS AJ24 D12
LVDS AK25 D14
LVDS AD21 D15
LVDS AE21 D17
LVDS AD27 D18
LVDS AD28 D20
LVDS AJ28 D21
LVDS AJ29 D23
D24
D26
D27
D29
D30
D31
D32
D33
D34
D35
D36
D38
D40
LVDS AG29 H1
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Chapter 1: KC705 Evaluation Board Features
Schematic Net Name
PWRCTL1_VCC4A_PG
FMC_LPC_GBTCLK0_M2C_P
FMC_LPC_GBTCLK0_M2C_N
FMC_LPC_LA01_CC_P
FMC_LPC_LA01_CC_N
FMC_LPC_LA05_P
FMC_LPC_LA05_N
FMC_LPC_LA09_P
FMC_LPC_LA09_N
FMC_LPC_LA13_P
FMC_LPC_LA13_N
FMC_LPC_LA17_CC_P
FMC_LPC_LA17_CC_N
FMC_LPC_LA23_P
FMC_LPC_LA23_N
FMC_LPC_LA26_P
FMC_LPC_LA26_N
FMC_LPC_TCK_BUF
FMC_HPC_TDO_LPC_TDI
FMC_LPC_TDO_FPGA_TDI
VCC3V3
FMC_LPC_TMS_BUF
NC
GA1=0=GND
VCC3V3
VCC3V3
VCC3V3
NC
Send Feedback
U1
I/O
FPGA
Standard
Pin
LVDS N8
LVDS N7
LVDS AE23
LVDS AF23
LVDS AG22
LVDS AH22
LVDS AK23
LVDS AK24
LVDS AB24
LVDS AC25
LVDS AB27
LVDS AC27
LVDS AH26
LVDS AH27
LVDS AK29
LVDS AK30
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