Ddr3 Memory Connections To The Fpga - Xilinx KC705 User Manual

Table 1-4: DDR3 Memory Connections to the FPGA
U1 FPGA
Pin
AH12
AG13
AG12
AF12
AJ12
AJ13
AJ14
AH14
AK13
AK14
AF13
AE13
AJ11
AH11
AK10
AK11
AH9
AG9
AK9
AA15
AA16
AC14
AD14
AA17
AB15
AE15
Y15
AB19
AD16
AC19
AD17
KC705 Evaluation Board
UG810 (v1.8) March 20, 2018
Net Name
DDR3_A0
DDR3_A1
DDR3_A2
DDR3_A3
DDR3_A4
DDR3_A5
DDR3_A6
DDR3_A7
DDR3_A8
DDR3_A9
DDR3_A10
DDR3_A11
DDR3_A12
DDR3_A13
DDR3_A14
DDR3_A15
DDR3_BA0
DDR3_BA1
DDR3_BA2
DDR3_D0
DDR3_D1
DDR3_D2
DDR3_D3
DDR3_D4
DDR3_D5
DDR3_D6
DDR3_D7
DDR3_D8
DDR3_D9
DDR3_D10
DDR3_D11
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Chapter 1: KC705 Evaluation Board Features
J1 DDR3 Memory
I/O Standard
Pin
Number
SSTL15 98
SSTL15 97
SSTL15 96
SSTL15 95
SSTL15 92
SSTL15 91
SSTL15 90
SSTL15 86
SSTL15 89
SSTL15 85
SSTL15 107
SSTL15 84
SSTL15 83
SSTL15 119
SSTL15 80
SSTL15 78
SSTL15 109
SSTL15 108
SSTL15 79
SSTL15 5
SSTL15 7
SSTL15 15
SSTL15 17
SSTL15 4
SSTL15 6
SSTL15 16
SSTL15 18
SSTL15 21
SSTL15 23
SSTL15 33
SSTL15 35
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Pin Name
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12_BC_N
A13
A14
A15
BA0
BA1
BA2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
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