Hpc Connections, J22 To Fpga U1 - Xilinx KC705 User Manual

34 LA pairs (LA00-LA33)
°
24 HA pairs (HA00-HA23)
°
• 4 GTX transceivers
• 2 GTX clocks
• 2 differential clocks
• 159 ground and 15 power connections
The HPC signals are distributed across GTX Quads 116, 117, and 118. Each of these Quads
have their VCCO voltage connected to VADJ.
The KC705 board VADJ voltage for the J22 and J2 connectors is determined by the FMC VADJ
Note:
power sequencing logic described in
Table 1-28: HPC Connections, J22 to FPGA U1
J22 Pin Schematic Net Name
A2 FMC_HPC_DP1_M2C_P
A3 FMC_HPC_DP1_M2C_N
A6 FMC_HPC_DP2_M2C_P
A7 FMC_HPC_DP2_M2C_N
A10 FMC_HPC_DP3_M2C_P
A11 FMC_HPC_DP3_M2C_N
A14 NC
A15 NC
A18 NC
A19 NC
A22 FMC_HPC_DP1_C2M_P
A23 FMC_HPC_DP1_C2M_N
A26 FMC_HPC_DP2_C2M_P
A27 FMC_HPC_DP2_C2M_N
A30 FMC_HPC_DP3_C2M_P
A31 FMC_HPC_DP3_C2M_N
A34 NC
A35 NC
A38 NC
A39 NC
KC705 Evaluation Board
UG810 (v1.8) March 20, 2018
Power Management, page
I/O FPGA
J22 Pin
Standard U1 Pin
D6 B1
D5 B4
B6 B5
B5 B8
A8 B9
A7 B12
B13
B16
B17
B20
C4 B21
C3 B24
B2 B25
B1 B28
A4 B29
A3 B32
B33
B36
B37
B40
www.xilinx.com
Chapter 1: KC705 Evaluation Board Features
71.
Schematic Net Name
NC
NC
NC
NC
NC
NC
NC
NC
NC
FMC_HPC_GBTCLK1_M2C_P
FMC_HPC_GBTCLK1_M2C_N
NC
NC
NC
NC
NC
NC
NC
NC
NC
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I/O FPGA
Standard U1 Pin
LVDS E8
LVDS E7
64