Gtx Transceivers - Xilinx KC705 User Manual

X-Ref Target - Figure 1-14
X5
114.285 MHz
20 ppm
2 XA
GND1
GND2 XB
4
GND
REC_CLOCK_C_P
R337
100Ω
REC_CLOCK_C_N
SI5326_INT_ALM
SI5326_RST
For more information about the Silicon Labs Si5324 see

GTX Transceivers

[Figure 1-2, callout 12]
The KC705 board provides access to 16 GTX transceivers:
• Eight of the GTX transceivers are wired to the PCI Express® x8 endpoint edge
connector (P1) fingers
• Four of the GTX transceivers are wired to the FMC HPC connector (J22)
• One GTX is wired to the FMC LPC connector (J2)
• One GTX is wired to SMA connectors (RX: J17, J18 TX: J19, J20)
• One GTX is wired to the SFP/SFP+ Module connector (P5)
• One GTX is used for the SGMII connection to the Ethernet PHY (U37)
KC705 Evaluation Board
UG810 (v1.8) March 20, 2018
SI5326_VCC
U70
5
10
32
1
SI5326_XTAL_XA 6
3
SI5326_XTAL_XB 7
C475
0.1μF 25V
X5R
REC_CLOCK_P 16
REC_CLOCK_N 17
NC 12
C476
0.1μF 25V
NC 13
X5R
3
NC 4
NC 11
NC 15
NC 18
NC 19
NC 20
1
21
R424
4.7KΩ 5%
GND
Figure 1-14: Jitter Attenuated Clock
www.xilinx.com
Chapter 1: KC705 Evaluation Board Features
Si5324C-C-GM
Clock Multiplier/
Jitter Attenuator
2
NC
VDDA NC1
2
NC
VDDA NC2
2
NC
VDDA NC3
5
NC
XA NC4
8
NC
NC5
29
SI5326_OUT_N
XB CKOUT1_N
28
SI5326_OUT_P
CKOUT1_P
35
NC
CKIN1_P
CKOUT2_N
34
NC
CKOUT2_P
CKIN1_N
CKIN2_P
CKIN2_N
37
GNDPAD
36
INT_C1B CMODE
27
C2B SDI
23
RATE0 SDA_SDO
22
RATE1 SCL
24
LOL A0
31
DEC A1
31
INC A2_SS
9
RST_B
GND1
31
CS_CA
GND2
GND
[Ref
C473
0.1μF 25V
X5R
SI5326_OUT_C_N
SI5326_OUT_C_P
C474
0.1μF 25V
X5R
NC
SI5326_SDA
SI5326_SCL
UG810_c1_14_031214
7].
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