Clock Generation; Kc705 Board Clock Sources; Clock Source To Fpga U1 Connections - Xilinx KC705 User Manual

Clock Generation

There are five clock sources available for the FPGA fabric on the KC705 board (refer to
Table 1-8).
Table 1-8: KC705 Board Clock Sources
Clock Name
System Clock
User Clock
User SMA Clock
(differential pair)
GTX SMA REF Clock
(differential pair)
Jitter Attenuated
Clock
Table 1-9 lists the pin-to-pin connections from each clock source to the FPGA.
Table 1-9: Clock Source to FPGA U1 Connections
Clock Source Pin
U6.5
U6.4
U45.5
U45.4
J12.1
J11.1
J15.1
J16.1
U70.29
U70.28
KC705 Evaluation Board
UG810 (v1.8) March 20, 2018
Reference
SiT9102 2.5V LVDS 200 MHz Fixed Frequency Oscillator (Si Time). See
U6
System Clock Source, page
Si570 3.3V LVDS I2C Programmable Oscillator
U45
(Silicon Labs). Default power-on frequency 156.250 MHz. See
Programmable User Clock Source, page
USER_SMA_CLOCK_P (net name).
J11
See User SMA Clock Input, page
USER_SMA_CLOCK_N (net name)
J12
See User SMA Clock Input, page 30
SMA_MGT_REFCLK_P (net name).
J16
See GTX SMA Clock Input, page
SMA_MGT_REFCLK_N (net name).
J15
See GTX SMA Clock Input, page
Si5324C LVDS precision clock multiplier/jitter attenuator (Silicon
Labs).
U70
See Jitter Attenuated Clock, page
Schematic Net Name
SYSCLK_N
SYSCLK_P
USER_CLOCK_N
USER_CLOCK_P
USER_SMA_CLOCK_N
USER_SMA_CLOCK_P
SMA_MGT_REFCLK_N
SMA_MGT_REFCLK_P
Si5326_OUT_N
Si5326_OUT_P
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Chapter 1: KC705 Evaluation Board Features
Description
29.
29.
30.
31.
31.
32.
I/O Standard
LVDS
LVDS
LVDS_25
LVDS_25
LVDS_25
LVDS_25
N/A (MGT REFCLK INPUT)
N/A (MGT REFCLK INPUT)
N/A (MGT REFCLK INPUT)
N/A (MGT REFCLK INPUT)
Send Feedback
U1 FPGA Pin
AD11
AD12
K29
K28
K25
L25
J7
J8
L7
L8
28