Lpc Connector J2 - Xilinx KC705 User Manual

Table 1-28: HPC Connections, J22 to FPGA U1 (Cont'd)
J22 Pin Schematic Net Name
J21 FMC_HPC_HA22_P
J22 FMC_HPC_HA22_N
J24 NC
J25 NC
J27 NC
J28 NC
J30 NC
J31 NC
J33 NC
J34 NC
J36 NC
J37 NC
J39 NC

LPC Connector J2

[Figure 1-2, callout 31]
The 160-pin LPC connector defined by the FMC specification
connectivity for up to:
• 68 single-ended or 34 differential user-defined signals
• 1 GTX transceiver
• 1 GTX clock
• 2 differential clocks
• 61 ground and 10 power connections
The connections between the LPC connector at J2 and FPGA U1
subset of this connectivity:
• 34 differential user defined pairs
34 LA pairs (LA00-LA33)
°
• 1 GTX transceiver
• 1 GTX clock
KC705 Evaluation Board
UG810 (v1.8) March 20, 2018
I/O FPGA
J22 Pin
Standard U1 Pin
LVDS L11 K20
LVDS K11 K22
K23
K25
K26
K28
K29
K31
K32
K34
K35
K37
K38
K40
www.xilinx.com
Chapter 1: KC705 Evaluation Board Features
Schematic Net Name
FMC_HPC_HA21_N
FMC_HPC_HA23_P
FMC_HPC_HA23_N
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
(Figure B-2, page
(Table 1-29) implement a
Send Feedback
I/O FPGA
Standard U1 Pin
LVDS J12
LVDS L12
LVDS L13
87) provides
68