Xilinx KC705 User Manual page 91

set_property IOSTANDARD SSTL15 [get_ports DDR3_D49]
set_property PACKAGE_PIN AE4 [get_ports DDR3_D50]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D50]
set_property PACKAGE_PIN AE3 [get_ports DDR3_D51]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D51]
set_property PACKAGE_PIN AF3 [get_ports DDR3_D52]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D52]
set_property PACKAGE_PIN AF5 [get_ports DDR3_D53]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D53]
set_property PACKAGE_PIN AE1 [get_ports DDR3_D54]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D54]
set_property PACKAGE_PIN AE5 [get_ports DDR3_D55]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D55]
set_property PACKAGE_PIN AC1 [get_ports DDR3_D56]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D56]
set_property PACKAGE_PIN AD3 [get_ports DDR3_D57]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D57]
set_property PACKAGE_PIN AC4 [get_ports DDR3_D58]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D58]
set_property PACKAGE_PIN AC5 [get_ports DDR3_D59]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D59]
set_property PACKAGE_PIN AE6 [get_ports DDR3_D60]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D60]
set_property PACKAGE_PIN AD6 [get_ports DDR3_D61]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D61]
set_property PACKAGE_PIN AC2 [get_ports DDR3_D62]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D62]
set_property PACKAGE_PIN AD4 [get_ports DDR3_D63]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D63]
#ADDRESS
set_property PACKAGE_PIN AH12 [get_ports DDR3_A0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A0]
set_property PACKAGE_PIN AG13 [get_ports DDR3_A1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A1]
set_property PACKAGE_PIN AG12 [get_ports DDR3_A2]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A2]
set_property PACKAGE_PIN AF12 [get_ports DDR3_A3]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A3]
set_property PACKAGE_PIN AJ12 [get_ports DDR3_A4]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A4]
set_property PACKAGE_PIN AJ13 [get_ports DDR3_A5]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A5]
set_property PACKAGE_PIN AJ14 [get_ports DDR3_A6]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A6]
set_property PACKAGE_PIN AH14 [get_ports DDR3_A7]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A7]
set_property PACKAGE_PIN AK13 [get_ports DDR3_A8]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A8]
set_property PACKAGE_PIN AK14 [get_ports DDR3_A9]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A9]
set_property PACKAGE_PIN AF13 [get_ports DDR3_A10]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A10]
set_property PACKAGE_PIN AE13 [get_ports DDR3_A11]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A11]
set_property PACKAGE_PIN AJ11 [get_ports DDR3_A12]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A12]
set_property PACKAGE_PIN AH11 [get_ports DDR3_A13]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A13]
KC705 Evaluation Board
UG810 (v1.8) March 20, 2018
Appendix C: Master Constraints File Listing
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91
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