Mode Switch - Xilinx KC705 User Manual

Figure 1-39 shows mode switch SW13.
X-Ref Target - Figure 1-39
FLASH_A25
FLASH_A24
FPGA_M2
FPGA_M1
FPGA_M0
The mode pins settings on SW13 determine if the Linear BPI or the Quad SPI flash memory
is used for configuring the FPGA. DIP switch SW13 also provides the upper two address bits
for the Linear BPI flash memory and can be used to select one of multiple stored
configuration bitstreams.
nonvolatile flash devices used for configuration and the FPGA.
To obtain the fastest configuration speed an external 66 MHz oscillator is wired to the
EMCCLK pin of the FPGA. This allows users to create bitstreams that configure the FPGA
over the 16-bit datapath from the Linear BPI flash memory at a maximum synchronous read
rate of 33 MHz. The bitstream stored in the flash memory must be generated with a BitGen
option to divide the EMCCLK by two.
KC705 Evaluation Board
UG810 (v1.8) March 20, 2018
R396 R398
1.21kΩ 1.21kΩ
0.1 W 0.1 W
1% 1%
R397 R399
1.21kΩ 1.21kΩ
0.1 W 0.1 W
1% 1%
GND
Figure 1-39: Mode Switch
Figure 1-40 shows the connectivity between the onboard
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Chapter 1: KC705 Evaluation Board Features
VCC2V5
R401
220Ω
0.1 W
SW13
1%
ON
1
10
9 2
8 3
7 4
6 5
SDA05H1SBD
R400
1.21kΩ
0.1 W
1%
UG810_c1_39_031214
Send Feedback
R402
220Ω
0.1 W
1%
81