Xilinx KC705 User Manual page 106

set_property PACKAGE_PIN U25 [get_ports PHY_RXD1]
set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXD1]
set_property PACKAGE_PIN T25 [get_ports PHY_RXD2]
set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXD2]
set_property PACKAGE_PIN U28 [get_ports PHY_RXD3]
set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXD3]
set_property PACKAGE_PIN R19 [get_ports PHY_RXD4]
set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXD4]
set_property PACKAGE_PIN T27 [get_ports PHY_RXD5]
set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXD5]
set_property PACKAGE_PIN T26 [get_ports PHY_RXD6]
set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXD6]
set_property PACKAGE_PIN T28 [get_ports PHY_RXD7]
set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXD7]
set_property PACKAGE_PIN V26 [get_ports PHY_RXER]
set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXER]
set_property PACKAGE_PIN R28 [get_ports PHY_RXCTL_RXDV]
set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXCTL_RXDV]
set_property PACKAGE_PIN M28 [get_ports PHY_TXCLK]
set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXCLK]
set_property PACKAGE_PIN N27 [get_ports PHY_TXD0]
set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXD0]
set_property PACKAGE_PIN N25 [get_ports PHY_TXD1]
set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXD1]
set_property PACKAGE_PIN M29 [get_ports PHY_TXD2]
set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXD2]
set_property PACKAGE_PIN L28 [get_ports PHY_TXD3]
set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXD3]
set_property PACKAGE_PIN J26 [get_ports PHY_TXD4]
set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXD4]
set_property PACKAGE_PIN K26 [get_ports PHY_TXD5]
set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXD5]
set_property PACKAGE_PIN L30 [get_ports PHY_TXD6]
set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXD6]
set_property PACKAGE_PIN J28 [get_ports PHY_TXD7]
set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXD7]
set_property PACKAGE_PIN N29 [get_ports PHY_TXER]
set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXER]
set_property PACKAGE_PIN K30 [get_ports PHY_TXC_GTXCLK]
set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXC_GTXCLK]
set_property PACKAGE_PIN M27 [get_ports PHY_TXCTL_TXEN]
set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXCTL_TXEN]
set_property PACKAGE_PIN W19 [get_ports PHY_COL]
set_property IOSTANDARD LVCMOS25 [get_ports PHY_COL]
set_property PACKAGE_PIN R30 [get_ports PHY_CRS]
set_property IOSTANDARD LVCMOS25 [get_ports PHY_CRS]
set_property PACKAGE_PIN N30 [get_ports PHY_INT]
set_property IOSTANDARD LVCMOS25 [get_ports PHY_INT]
set_property PACKAGE_PIN R23 [get_ports PHY_MDC]
set_property IOSTANDARD LVCMOS25 [get_ports PHY_MDC]
set_property PACKAGE_PIN J21 [get_ports PHY_MDIO]
set_property IOSTANDARD LVCMOS25 [get_ports PHY_MDIO]
set_property PACKAGE_PIN L20 [get_ports PHY_RESET]
set_property IOSTANDARD LVCMOS25 [get_ports PHY_RESET]
set_property PACKAGE_PIN H5 [get_ports SGMII_RX_N]
set_property PACKAGE_PIN H6 [get_ports SGMII_RX_P]
set_property PACKAGE_PIN J3 [get_ports SGMII_TX_N]
set_property PACKAGE_PIN J4 [get_ports SGMII_TX_P]
set_property PACKAGE_PIN G7 [get_ports SGMIICLK_Q0_N]
KC705 Evaluation Board
UG810 (v1.8) March 20, 2018
Appendix C: Master Constraints File Listing
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