Viavi Xgig User Manual page 37

Launching Xgig TraceControl
• FEC Locked - Indicates whether the port was able to detect the FEC and lock into it
To show this column, right-click a column header, and select
Transmission Columns
• FEC Parity Err - This is an error counter for errors detected by FEC.
To show this column, right-click a column header, and select
Error Columns
CDR
The CDR (Clock Data Recovery) column is hidden by default. See
on page 105.
Note that the running time of the capture is provided in the right corner of the status bar.
Link Monitoring in Port Status View
When ports are aggregated into links, links appear as a separate row within the status view. The
same status fields (columns) are used for a link, but some fields have a slightly different meaning
and some are not used.
Port Name
The name identifying the link. If the link has been given a user-defined name, the user-defined
name will appear in this column.
B/W, F/P (LEDs)
See the table below for the definition of LED colors for links. The LEDs for links are slightly
different than for individual ports as it indicates a status for the entire link. A tooltip showing the
B/W or F/P status or errors for a link appears when you curse over the LED.
Table 3: Word and Frame Status LEDs for Links
Byte/Word LED
Gray
Black
Red
Yellow
Green
Frame/Packet LED
Black
Gray
Red
Yellow
Green
Xgig Analyzer User's Guide
.
.
Reason
Ports in link are not locked
No signal or no light for all ports
At least one port in the link has a signal with errors; for example, illegal characters,
running disparity violations, CRC mis-match
At least one port in the link has had an error in the past, currently no ports have
errors
All ports free of errors. At least one port in the link has a good signal, legal
characters, proper disparity, good CRC if present
Reason
No SOF ordered set recognized for all ports
Ports in link are not locked
At least one port in the link has an SOF with CRC mismatch error
At least one port in the link had a CRC error in the past, currently no errors for all
ports in the link
All ports free of errors. At least one port in the link has a good CRC and recognized
SOFs are present
Chapter 3, Getting Started with Xgig TraceControl
Add/Remove Columns
Add/Remove Columns
"CDR (Clock Data Recovery)"
>
Data
>
Phy
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