Configuration - ABB REL650 Applications Manual

1MRK 506 334-UUS A
13.4.3.1
Application manual
Both timers in the same logic block (the one delayed on pick-up and the one delayed on
drop-out) always have a common setting value.
For controllable gates, settable timers and SR flip-flops with memory, the setting
parameters are accessible via the local HMI or via the PST tool.

Configuration

Logic is configured using the ACT configuration tool in PCM600.
Execution of functions as defined by the configurable logic blocks runs according to a
fixed sequence with different cycle times.
For each cycle time, the function block is given an serial execution number. This is shown
when using the ACT configuration tool with the designation of the function block and the
cycle time, see example below.
IEC09000695 V2 EN
Figure 205: Example designation, serial execution number and cycle time for logic
function
The execution of different function blocks within the same cycle is determined by the
order of their serial execution numbers. Always remember this when connecting two or
more logical function blocks in series.
Always be careful when connecting function blocks with a fast cycle time
to function blocks with a slow cycle time.
Remember to design the logic circuits carefully and always check the
execution sequence for different functions. In other cases, additional time
delays must be introduced into the logic schemes to prevent errors, for
example, race between functions.
Default value on all four inputs of the AND gate are logical 1 which makes
it possible for the user to just use the required number of inputs and leave
the rest un-connected. The output OUT has a default value 0 initially,
IEC09000695_2_en.vsd
Section 13
Logic
421