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The PD75402A has a standby function which can reduce the system power consumption. The standby function
has the following two modes:
• STOP mode
• HALT mode
(1) STOP mode
In this mode, the main system clock oscillator is stopped and the whole system stops. The CPU current drain is
reduced considerably.
Data memory low voltage (up to V
the contents of data memory at an ultra-low current drain.
The PD75402A STOP mode cannot be reset by interrupt request. It is reset only by RESET input.
(2) HALT mode
This mode stops the CPU operation clock. The system clock oscillator continues to oscillate. In this mode, the
current drain is not reduced as much as the STOP mode, but this mode is effective when desiring to resume
processing immediately by interrupt request and when desiring to perform intermittent operation, such as timer
operation.
The HALT mode is reset by RESET input or interrupt request.
In either mode, the contents of the registers, flags, and data memory immediately before setting to the standby
mode are retained. Because the states of the I/O port output latch and the output buffer are retained, the state of
the I/O ports is preprocessed so that the current drain of the entire system is minimum.
Note
1. Low current, low voltage operation is possible by switching the standby mode and CPU clock. However,
in either case, the time described in paragraph 5.2.3 is necessary between operation of the PCC register
and selection of the new clock and the start of operation by the new clock after switching. Therefore,
when combining the clock switching function and standby mode, set the PD75402A to the standby
mode after the time required for switching has elapsed.
2. When using the standby mode, ensure that the consumption current at the input/output is a minimum.
In particular, do not leave the input port open : be sure to input a low-level or high-level signal.
CHAPTER 7. STANDBY FUNCTION
CHAPTER 7. STANDBY FUNCTION
= 2 V) hold is also possible. Therefore, this mode is effective when retaining
DD
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