Clock Domains; Bit Sequences; Validation Errors/Warnings; Ibis-Ami Model Control Parameters - Xilinx virtex-5 fpga User Manual

IBIS-AMI Model Control Parameters

Clock Domains

A number of pre-defined clock speeds are included in this kit:
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•
•
•
•
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Bit Sequences

This kit uses the default Quantum Channel Designer stimulus and pattern definitions.
Bit sequences can be edited by selecting Setup  Bit Sequence from the Quantum
Channel Designer GUI.

Validation Errors/Warnings

This interface validates with zero errors and zero warnings.
IBIS-AMI Model Control Parameters
Table 1-9
included in this kit.
Table 1-9: Model Parameters
TX Model Parameters
12
SerDes_1p25G = 800 ps
SerDes_1p5G = 666 ps
SerDes_2p5G = 400 ps
SerDes_3p0G = 333 ps
SerDes_3p125G = 320 ps
SerDes_3p75G = 266 ps
defines the GUI parameters that control the IBIS-AMI algorithmic models
Parameter
This parameter controls the output's voltage swing. Allowable
settings are:
"000: 1100mV"
"001: 1050mV"
"010: 1000mV"
TX_Strength
(TXDIFFCTRL) "011: 900mV"
"100: 800mV"
"101: 600mV"
"110: 400mV"
"111
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Description
: 0mV"
Virtex-5 FPGA GTP Transceiver SIS Kit (IBIS-AMI)
UG587 (v1.1) June 21, 2012