Chapter 2: Shared Features; Reference Clock Input Structure - Xilinx 7 Series User Manual

Shared Features

Reference Clock Input Structure

Functional Description
The reference clock input structure is illustrated in
with 50Ω on each leg to 4/5 MGTAVCC. The reference clock is instantiated in software with the
IBUFDS_GTE2 software primitive. The ports and attributes controlling the reference clock input
are tied to the IBUFDS_GTE2 software primitive.
Figure 2-1
X-Ref Target - Figure 2-1
MGTAVCC = 1.0V
MGTAVSS
I
MGTREFCLK[0/1]P
MGTREFCLK[0/1]N
CLKRCV_TRST
IB
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
shows the internal structure of the reference clock input buffer.
Nominal 50
CLKCM_CFG
+
4/5
-
MGTAVCC
Nominal 50
CEB
Figure 2-1: Reference Clock Input Structure
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Chapter 2
Figure 2-1. The input is terminated internally
TO GTREFCLK0/1 of
GTPE2_COMMON
2'b00
/2 2'b01
REFCLK_CTRL[1:0]
1'b0 2'b10
Reserved 2'b11
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O
TO HROW
ODIV2
UG482_c2_01_112811
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