Setting The Maximum Skew - Xilinx 7 Series User Manual

X-Ref Target - Figure 4-51
CHAN_BOND_SEQ_x_4

Setting the Maximum Skew

When the master receives a channel bonding sequence, it does not trigger channel bonding
immediately. Several more bytes must arrive if the slaves have more latency. This wait time
effectively becomes the maximum skew that the RX elastic buffer can handle. If the skew is greater
than this wait time, the slaves might not receive the sequence by the time the master triggers channel
bonding.
Figure 4-52
master, the master must wait several cycles before triggering channel bonding, otherwise the slow
slave does not have the channel bonding sequence in its buffer.
X-Ref Target - Figure 4-52
Master receives CB Sequence
The master waits CHAN_BOND_MAX_SKEW
cycles before triggering channel bonding, giving
the slave time to receive the sequence. The
message to perform channel bonding is sent
using the RXCHBONDO port.
The RXCHANBONDLEVEL setting of the master
determines how many cycles later the bonding
operation is executed. At this time, the slave's
elastic buffer pointers are moved so that the
output is deskewed.
Figure 4-52: Channel Bonding Example (CHAN_BOND_MAX_SKEW = 2 and
CHAN_BOND_MAX_SKEW is used to set the maximum skew allowed for channel bonding
sequences 1 and 2. The maximum skew range is 1 to 14. This range must always be less than
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
CHAN_BOND_SEQ_x_3
CHAN_BOND_SEQ_x_ENABLE
Figure 4-51: Channel Bonding Sequence Mapping
shows two FIFOs, one for the master and one for the slave. If the slave is behind the
SEQ1 D7
D7 D6
D10 D9
D9 D8
D11 D10
D10 D9
Master RXCHANBONDLEVEL[2:0] = 1)
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CHAN_BOND_SEQ_x_2
4 3 2 1
D6 D5 D4 D3
D5 D4 D3 D2
D8 SEQ1 D7 D6
SEQ1 D7 D6 D5
D9 D8 SEQ1 D7
D8 SEQ1 D7 D6
Slave's New Elastic
Buffer Read Pointer
RX Channel Bonding
CHAN_BOND_SEQ_x_1
UG482_c4_33_111011
Master
D2 D1
Elastic
Buffer
Slave
D1 D0
Elastic
Buffer
Master
D5 D4
Elastic
Buffer
Slave
D4 D3
Elastic
Buffer
Master
D6 D5
Elastic
Buffer
Slave
D5 D4
Elastic
Buffer
UG482_c4_34_111011
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