Using The Tx Phase Alignment Circuit To Minimize Tx Skew - Xilinx Virtex-5 RocketIO GTP User Manual

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It is critical that the shared PMA clock and TXUSRCLK both be stable before phase
alignment is attempted:
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Using the TX Phase Alignment Circuit to Minimize TX Skew

The phase-alignment procedure can also be used to minimize TX skew between GTP
transceivers. For phase alignment to be effective, TXUSRCLK for all the GTP transceivers
must come from the same source, and must be routed through a low-skew clocking
resource (a BUFG or a BUFR).
driven for low-skew operation. The same restrictions that apply to TX phase alignment for
buffer bypass also apply to phase alignment for low skew.
.
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
PLLLKDET
TXENPHASEALIGN
TXPMASETPHASE
Figure 6-12: TX PMACLK Phase-Alignment Procedure
If REFCLKOUT drives TXUSRCLK directly, wait for PLLLKDET to be asserted before
phase aligning.
If TXUSRCLK comes from a DCM or PLL, wait for PLLLKDET and the LOCKED
signal from the DCM or PLL before phase aligning.
GTP
TXUSRCLK
Transceiver
TXUSRCLK
GTP
Transceiver
Figure 6-13: TX Low-Skew Phase-Alignment Configuration
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TX Buffering, Phase Alignment, and Buffer Bypass
512 TXUSRCLK2 cycles
Required TXUSRCLK2 cycles
Figure 6-13 shows how the TXUSRCLK signals must be
BUFG or
BUFR
UG196_c6_12_051407
REFCLKOUT
Dividers
(if necessary)
UG196_c6_13_030507
107